82P2288BB8 IDT, Integrated Device Technology Inc, 82P2288BB8 Datasheet - Page 22

• Manufacturer Part Number: 82P2288BB8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB8

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

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E1/J1 trunks. Each link of the IDT82P2288 can be independently config-
ured. The configuration is performed through an SPI or parallel micro-
processor interface.
LINE INTERFACE - RECEIVE PATH
RTIPn and RRINGn pins and pass through an Impedance Terminator.
An Adaptive Equalizer is provided to increase the sensitivity for small
signals. Clock and data are recovered from the digital pulses output from
the slicer. After passing through the Receive Jitter Attenuator (can be
enabled or disabled), the recovered data is decoded using B8ZS (for T1/
J1) / HDB3 (for E1) or AMI line code rules and clocked into the Frame
Processor. Loss of signal, line code violations and excessive zero are
detected.
FRAMER - RECEIVE PATH
configured in Super Frame (SF), Extended Super Frame (ESF), T1
Digital Multiplexer (DM) or Switch Line Carrier - 96 (SLC-96) formats.
(The T1 DM and SLC-96 formats only exist in T1 mode). The framing
can also be bypassed (unframed mode). The Framer detects and indi-
cates the out of SF/ESF/DM/SLC-96 synchronization event, the Yellow,
Red and AIS alarms. The Framer also detects the presence of inband
loopback codes and bit-oriented messages. Frame Alignment Signal
errors, CRC-6 errors, out of SF/ESF/T1 DM/SLC-96 events and Frame
Alignment position changes are counted. Up to three HDLC links (in
ESF and T1 DM format) or two HDLC links (in SF and SLC-96 format)
are provided to extract the HDLC message on the DL bit (in ESF format)
/ D bit in CH24 (in T1 DM format) or any arbitrary position. In the T1/J1
receive path, signaling debounce, signaling freeze, idle code substitu-
tion, digital milliwatt code insertion, idle code insertion, data inversion
and pattern generation or detection are supported on a per-channel
basis. An Elastic Store Buffer that supports controlled slip and adapta-
tion to backplane timing may be enabled. In the Receive System Inter-
face, various operating modes can be selected to output signals to the
system.
ured to frame to Basic Frame, CRC Multi-Frame and Signaling Multi-
Frame. The framing can be bypassed (unframed mode). The Framer
detects and indicates the following event: out of Basic Frame Sync, out
of CRC Multi-Frame, out of Signaling Multi-Frame, Remote Alarm Indi-
cation signal and Remote Signaling Multi-Frame Alarm Indication signal.
The Framer also monitors Red and AIS alarms. Basic Frame Alignment
Signal errors, Far End Block Errors (FEBE) and CRC errors are
counted. Up to three HDLC links are provided to extract the HDLC
message on TS16, the Sa National bits or any arbitrary timeslot. In the
E1 receive path, signaling debounce, signaling freezing, idle code
substitution, digital milliwatt code insertion, trunk conditioning, data
inversion and pattern generation or detection are also supported on a
per-timeslot basis. An Elastic Store Buffer that supports slip buffering
Functional Description
IDT82P2288
The IDT82P2288 is a highly featured single device solution for T1/
In the receive path, the signals from the line side are coupled into the
In T1/J1 Mode, the recovered data and clock of each link can be
In E1 Mode, the recovered data and clock of each link can be config-
FUNCTIONAL DESCRIPTION
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OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
and adaptation to backplane timing may be enabled. In the Receive
System Interface, various operating modes can be selected to output
signals to the system.
SYSTEM INTERFACE
1.544 Mbit/s can be converted to/from the data stream of 2.048 Mbit/s
by software configuration. In addition, the eight links can be grouped into
two sets with four links in each set. Each set can be multiplexed to or de-
multiplexed from one of the two 8.192 Mbit/s buses. If the device is in E1
mode, four of the eight links can be multiplexed to or de-multiplexed
from one of the two 8.192 Mbit/s buses.
FRAMER - TRANSMIT PATH
with various operating modes. In T1/J1 mode, the signals can be
processed by a Transmit Payload Control to execute the signaling inser-
tion, idle code substitution, data insertion, data inversion and test pattern
generation or detection on a per-channel basis. The transmit path of
each transceiver can be configured to generate SF, ESF, T1 DM or SLC-
96. The framer can also be disabled (unframed mode). The Framer can
transmit Yellow alarm and AIS alarm. Inband loopback codes and bit
oriented message can be transmitted. Up to three HDLC links (in ESF
and T1 DM format) or two HDLC links (in SF and SLC-96 format) are
provided to insert the HDLC message on the DL bit (in ESF format) / D
bit in CH24 (in T1 DM format) or any arbitrary position. After passing
through a Transmit Buffer, the processed data and clock are input to the
Encoder.
Control to execute the signaling insertion, idle code substitution, data
insertion, data inversion and test pattern generation or detection on a
per-timeslot basis. The transmit path of each transceiver can be config-
ured to generate Basic Frame, CRC Multi-Frame and Signaling Multi-
Frame. The framer can be disabled (unframed mode). The Framer can
transmit Remote Alarm Indication signal, the Remote Signaling Multi-
Frame Alarm Indication signal, AIS alarm and FEBE. Three HDLC links
are provided to insert the HDLC message on TS16, the Sa National bits
or any arbitrary timeslot. The processed data and clock are input to the
Encoder.
LINE INTERFACE - TRANSMIT PATH
E1) line code rules. The Transmit Jitter Attenuator, if enabled, is
provided with a FIFO in the transmit data path. A de-jittered clock is
generated by an integrated digital phase-locked loop and is used to read
data from the FIFO. The shapes of the pulses are user programmable to
ensure that the T1/E1/J1 pulse template is met after the signal passing
through different cable lengths and types. Bipolar violation can be
inserted for diagnostic purposes if AMI line code rule is enabled. The
signal is transmitted on the TTIPn and TRINGn pins through an Imped-
ance Terminator.
On the system side, if the device is in T1/J1 mode, the data stream of
In the transmit path, the Transmit System Interface inputs the signals
In E1 mode, the signals can be processed by a Transmit Payload
The data is encoded using AMI or B8ZS (for T1/J1) and HDB3 (for
March 04, 2009