82P2288BB8 IDT, Integrated Device Technology Inc, 82P2288BB8 Datasheet - Page 228

• Manufacturer Part Number: 82P2288BB8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82P2288BB8

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

5.2.1.2 Indirect Register
PMON:
T1/J1 CRCE Counter Mapping 0 (00H)
CRCE[7:0]:
T1/J1 CRCE Counter Mapping 1 (01H)
CRCE[9:8]:
T1/J1 FER Counter Mapping 0 (02H)
FER[7:0]:
Programming Information
IDT82P2288
Bit Name
Bit Name
Bit Name
The PMON Counter Mapping Registers (00H ~ 0BH) of a link are updated as a group in the following ways:
• A transition from ‘0’ to ‘1’ on the UPDAT bit (b1, T1/J1-0C2H,...) updates all the registers;
• If the AUTOUPD bit (b0, T1/J1-0C2H,...) is set to ‘1’, the registers will be updated every one second;
In ESF format, these bits together with the CRCE[9:8] bits count the CRC-6 Error numbers. The CRCE[0] bit is the LSB.
In ESF format, these bits together with the CRCE[7:0] bits count the CRC-6 Error numbers. The CRCE[9] bit is the MSB.
In SF / T1 DM / SLC-96 format, these bits together with the FER[11:8] bits count the F Bit Error numbers. The FER[0] bit is the LSB.
In ESF format, these bits together with the FER[11:8] bits count the Frame Alignment Bit Error numbers. The FER[0] bit is the LSB.
Default
Default
Bit No.
Bit No.
Bit No.
Type
Type
Type
R
CRCE7
FER7
R
R
7
0
7
7
0
CRCE6
FER6
R
R
6
0
6
6
0
CRCE5
FER5
R
R
5
0
5
5
0
Reserved
CRCE4
FER4
R
R
4
0
4
4
0
228
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
CRCE3
FER3
R
R
3
0
3
3
0
CRCE2
FER2
R
R
2
0
2
2
0
CRCE1
CRCE9
FER1
R
R
R
1
0
1
0
1
0
March 04, 2009
CRCE0
CRCE8
FER0
R
R
R
0
0
0
0
0
0