DJLXT380LE.B4 Cortina Systems Inc, DJLXT380LE.B4 Datasheet
DJLXT380LE.B4
Specifications of DJLXT380LE.B4
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DJLXT380LE.B4 Summary of contents
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LXT380 Octal E1 Line Interface Unit The LXT380 is an octal short haul Pulse Code Modulation (PCM) Line Interface Unit for ITU G.703 2.048 Mbit/sec. transmission systems. It incorporates eight independent receivers and eight independent transmitters in a single LQFP-144 ...
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Information in this document is provided in connection with Intel property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express ...
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Contents 1.0 Pin Assignments and Signal Descriptions 2.0 Functional Description 2.1 Initialization..........................................................................................................21 2.1.1 Reset Operation .....................................................................................21 2.2 Receiver ..............................................................................................................21 2.2.1 Loss Of Signal Detector .........................................................................22 2.2.1.1 Clock and Data Recovery Mode................................................22 2.2.1.2 Data Recovery Mode.................................................................22 2.3 In Service Code Violation ...
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LXT380 — Octal E1 Line Interface Unit 6.0 Mechanical Specifications Figures 1 LXT380 Block Diagram ......................................................................................... 7 2 LXT380 Detailed Block Diagram ........................................................................... 8 3 LXT380 Low-Profile Quad Flat Package (LQFP) Pin Assignments ...................... 9 4 LXT380 Plastic Ball Grid ...
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LOS Status Monitor Register (04H).....................................................................35 11 DFM Status Monitor Register (05H) ....................................................................35 12 LOS Interrupt Enable Register (06H) ..................................................................35 13 DFM Interrupt Enable Register (07H)..................................................................35 14 LOS Interrupt Status Register (08H) ...................................................................35 15 DFM Interrupt Status Register (09H)...................................................................35 16 ...
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LXT380 — Octal E1 Line Interface Unit Revision History Revision Date 6 Description Datasheet ...
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Applications E1 digital cross connects SDH E1 tributary interfaces Figure 1. LXT380 Block Diagram JTAG SERIAL/ PARALLEL PORT RTIP RRING TTIP TRING Datasheet Octal E1 G.703 Transceiver — LXT380 Public switching trunk line interfaces Microwave transmission systems HARDWARE / SOFTWARE ...
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LXT380 — Octal E1 G.703 Transceiver Figure 2. LXT380 Detailed Block Diagram JTAG SERIAL/ PARALLEL PORT RTIP7 RRING7 TTIP7 TRING7 RTIP6/RRING6 TTIP6/TRING6 RTIP5/RRING5 TTIP5/TRING5 RTIP4/RRING4 TTIP4/TRING4 RTIP3/RRING3 TTIP3/TRING3 RTIP2/RRING2 TTIP2/TRING2 RTIP1/RRING1 TTIP1/TRING1 RTIP0 MUX RRING0 TTIP0/TRING0 ...
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Pin Assignments and Signal Descriptions Figure 3. LXT380 Low-Profile Quad Flat Package (LQFP) Pin Assignments and Package Markings TPOS7/TDATA7 1 TCLK7 2 LOS6 3 RNEG6/BPV6 4 5 RPOS6/RDATA6 RCLK6 6 TNEG6/UBS6 7 TPOS6/TDATA6 8 TCLK6 9 MCLK 10 11 ...
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LXT380 — Octal E1 G.703 Transceiver Figure 4. LXT380 Plastic Ball Grid Array (PBGA) Package Pin Assignments RCLK RPOS RNEG TVCC TCLK TPOS TNEG TVCC RCLK ...
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Table 1. LXT380 Pin Description Pin # Pin # Symbol I/O LQFP PBGA 1 B2 TPOS7 1 B2 TDATA7 2 B1 TCLK7 3 E3 LOS6 RNEG6 4 C3 BPV6 4 C3 RPOS6 5 C2 RDATA ...
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LXT380 — Octal E1 G.703 Transceiver Table 1. LXT380 Pin Description Pin # Pin # Symbol I/O LQFP PBGA 7 D3 TNEG6 7 D3 UBS6 8 D2 TPOS6 8 D2 TDATA6 9 D1 TCLK6 10 E1 MCLK 11 E2 MODE ...
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Table 1. LXT380 Pin Description Pin # Pin # Symbol I/O LQFP PBGA VCCIO0 GNDIO VCC0 20 H4 GND0 † DI: ...
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LXT380 — Octal E1 G.703 Transceiver Table 1. LXT380 Pin Description Pin # Pin # Symbol I/O LQFP PBGA LOOP0/ D0 LOOP1 LOOP2 LOOP3 LOOP4 ...
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Table 1. LXT380 Pin Description Pin # Pin # Symbol I/O LQFP PBGA RPOS0 40 P2 RDATA RNEG0 41 P3 BPV0 42 K4 LOS0 43 K2 MUX N4, 44 TVCC0 TTIP0 46 ...
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LXT380 — Octal E1 G.703 Transceiver Table 1. LXT380 Pin Description Pin # Pin # Symbol I/O LQFP PBGA N9, 62 TGND3 P9 63 P10 TRING3 64 N10 TTIP3 N11, 65 TVCC3 P11 RRING RTIP3 ...
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Table 1. LXT380 Pin Description Pin # Pin # Symbol I/O LQFP PBGA 83 K14 ACK 83 K14 RDY 83 K14 SDO 84 J14 DS 84 J14 WR 84 J14 SDI 85 J13 R/W 85 J13 RD 86 J12 ALE ...
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LXT380 — Octal E1 G.703 Transceiver Table 1. LXT380 Pin Description Pin # Pin # Symbol I/O LQFP PBGA 94 H13 AT1 95 G12 TRST 96 F11 TMS 97 F14 TCK 98 F13 TDO 99 F12 TDI 100 D14 TCLK5 ...
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Table 1. LXT380 Pin Description Pin # Pin # Symbol I/O LQFP PBGA 115 E13 CLKE A11, 116 TVCC4 B11 117 B10 TTIP4 118 A10 TRING4 119 A9, B9 TGND4 RTIP4 120 A8 RRING 121 B8 4 C9, 122 TGND5 ...
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LXT380 — Octal E1 G.703 Transceiver Table 1. LXT380 Pin Description Pin # Pin # Symbol I/O LQFP PBGA RRING 138 B7 7 139 A7 RTIP7 140 E4 LOS7 RNEG7 141 A3 BPV7 141 A3 RPOS7 142 A2 RDATA 142 ...
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Functional Description Figure 4 on page 10 interface unit designed for G.703 2.048 Mbps applications. Each transceiver front end interfaces with four lines, one pair for transmit, one pair for receive. These two lines comprise a digital data loop ...
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LXT380 — Octal E1 G.703 Transceiver 2.2.1 Loss Of Signal Detector The loss of signal detector in the LXT380 uses a dedicated analog and digital loss of signal detection circuit independent of its internal data slicer comparators. and ...
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Transmitter The eight low power transmitters of the LXT380 are identical. Transmit data applied to TPOS/TNEG is clocked serially into the device. Input synchronization is supplied by the transmit clock (TCLK). The TPOS/TNEG inputs are sampled on the falling ...
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LXT380 — Octal E1 G.703 Transceiver 2.5 Line Protection As shown in Figure into the device. Due to the high receiver impedance (70 k typical), the resistors do not affect the receiver sensitivity. In the transmit side, Schottky diodes D1-D4 ...
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Driver Failure Monitor The LXT380 transceiver incorporates a unique internal smart power Driver Failure Monitor (DFM) in parallel with TTIP and TRING that is capable of detecting secondary line shorts. This feature is available in the serial and parallel ...
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LXT380 — Octal E1 G.703 Transceiver 2.7.2 Digital Loopback The digital loopback function is available in host mode only. When selected, the transmit clock and data inputs (TCLK, TPOS & TNEG) are looped back and output on the RCLK, RPOS ...
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Transmit All Ones (TAOS) In Hardware mode, the TAOS mode is set by pulling TCLK High for more than 16 MCLK cycles. In host mode, TAOS mode is set by asserting the corresponding bit in the TAOS Register. In ...
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LXT380 — Octal E1 G.703 Transceiver 2.8 G.772 Monitoring The LXT380 can be configured as an octal line interface unit with all channels working as regular transceivers. In applications using only seven channels, the eight channel can be configured to ...
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Table 2. Operation Mode Summary MCLK TCLK L Clocked L Clocked Clocked H Clocked H Clocked † Hardware mode only. 2.11 ...
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LXT380 — Octal E1 G.703 Transceiver generator that controls an Intel and Motorola compatible handshake output signal (RDY/ACK). In Motorola mode, ACK Low signals valid information is on the data bus. During a write cycle a Low signal acknowledges the ...
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Interrupt Handling 2.13.1 Interrupt Sources There are two interrupt sources: 1. Status change in the Loss of Signal (LOS) status register (04H.) The LXT380’S analog/digital loss of signal processor continuously monitors the receiver signal and updates the specific LOS ...
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LXT380 — Octal E1 G.703 Transceiver 2.14 Serial Host Mode The LXT380 operates in Serial Host Mode when the MODE pin is left open. SIO data structure. The registers are accessible through a 16bit word: an 8bit Command/Address byte (bits ...
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Register Descriptions Table 4. Serial and Parallel Port Register Addresses Name ID Register Analog Loopback Remote Loopback TAOS Enable LOS Status Monitor DFM Status Monitor LOS Interrupt Enable DFM Interrupt Enable LOS Interrupt Status DFM Interrupt Status Software Reset ...
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LXT380 — Octal E1 G.703 Transceiver Table 5. Register Addresses and Bit Names (Continued) Register Name Sym LOS Interrupt LIS Status DFM Interrupt DIS Status Software Reset RES Register Performance MON Monitoring Digital DL Loopback LOS Criteria LCS Select Automatic ...
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Table 10. LOS Status Monitor Register (04H) Bit Name 7-0 LOS7-LOS0 Table 11. DFM Status Monitor Register (05H) Bit Name 7-0 DFM7-DFM0 Table 12. LOS Interrupt Enable Register (06H) Bit Name 7-0 LIE7-LIE0 Table 13. DFM Interrupt Enable Register (07H) ...
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LXT380 — Octal E1 G.703 Transceiver Table 17. Performance Monitoring Register Bit Name Protected Monitoring Select reserved 5 reserved 6 reserved 7 reserved Table 18. Digital Loopback Register (0CH) Bit Name ...
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JTAG Boundary Scan 4.1 Overview The LXT380 supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy access to the interface pins for board testing purposes. In addition to the traditional IEE1149.1 digital boundary scan capabilities, the LXT380 ...
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LXT380 — Octal E1 G.703 Transceiver 4.3 TAP Controller The TAP controller state synchronous state machine controlled by the TMS input and clocked by TCK. See an instruction, receiving data, transmitting data idle state. ...
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Figure 15. JTAG State Diagram 1 TEST-LOGIC RESET RUN TEST/IDLE Datasheet Octal E1 G.703 Transceiver — LXT380 1 SELECT- CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE-DR 1 ...
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LXT380 — Octal E1 G.703 Transceiver 4.4 JTAG Register Description The following paragraphs describe each of the registers represented in 4.4.1 Boundary Scan Register, BSR The BSR is a shift register that provides access to all the digital I/O pins. ...
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Table 22. Boundary Scan Register, BSR (Continued) Pin Bit # I/O Type Signal 24 LOS1 25 TCLK0 26 TPOS0 27 TNEG0 28 RCLK0 29 RPOS0 30 RNEG0 31 N/A 32 LOS0 33 MUX 34 LOS3 35 RNEG3 36 RPOS3 37 ...
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LXT380 — Octal E1 G.703 Transceiver Table 22. Boundary Scan Register, BSR (Continued) Pin Bit # I/O Type Signal 24 LOS1 25 TCLK0 26 TPOS0 27 TNEG0 28 RCLK0 29 RPOS0 30 RNEG0 31 N/A 32 LOS0 33 MUX 34 ...
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Table 22. Boundary Scan Register, BSR (Continued) Pin Bit # I/O Type Signal MOT/ INTL 58 TCLK5 59 TPOS5 60 TNEG5 61 RCLK5 62 RPOS5 63 RNEG5 64 N/A 65 LOS5 66 TCLK4 67 TPOS4 68 TNEG4 ...
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LXT380 — Octal E1 G.703 Transceiver Table 22. Boundary Scan Register, BSR (Continued) Pin Bit # I/O Type Signal 88 RCLK6 89 TNEG6 90 TPOS6 91 TCLK6 92 MCLK 93 MODE 94 GND ...
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Analog Port Scan Register, ASR The ASR bit shift register used to control the analog test port at pins AT1, AT2. When the INTEST_ANALOG instruction is selected, TDI connects to the ASR input and TDO connects ...
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LXT380 — Octal E1 G.703 Transceiver The Analog Test Port can be used to verify continuity across the coupling transformer’s primary winding. By applying a stimulus to the AT1 input, a known voltage will appear at AT2 for a given ...
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Test Specifications Table 25. Instruction Register, IR Instruction EXTEST INTEST_ANALOG SAMPLE / PRELOAD IDCODE BYPASS Note: Tables 26 through 41 LXT380 and are guaranteed by test except, where noted, by design. The minimum and maximum values listed in Tables ...
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LXT380 — Octal E1 G.703 Transceiver Table 26. Absolute Maximum Ratings (Continued) Parameter Maximum package power dissipation Thermal resistance, junction to ambient, 144 pin LQFP package Thermal resistance, junction to ambient, 160 pin PBGA package Caution: Exceeding these values may ...
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Table 28. DC Characteristics (Continued) Parameter Low level input voltage Midrange level input voltage MODE and LOOP High level input 0-7 voltage Low level input current High level input current Input leakage current Tri state leakage current Tri state output ...
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LXT380 — Octal E1 G.703 Transceiver Table 29. Transmit Transmission Characteristics (Continued) Parameter 51kHz to 102 kHz Transmit 102 kHz to 2.048 return loss MHz 75 † 2.048 MHz to coaxial 3.072 MHz Transmit 51kHz to 102 kHz return 102 ...
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Table 30. Receive Transmission Characteristics (Continued) Parameter LOS delay time LOS reset Receive intrinsic jitter † Guaranteed by design and other correlation methods. Table 31. Analog Test Port Characteristics Parameter 3 dB bandwidth Input voltage range Output voltage range Table ...
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LXT380 — Octal E1 G.703 Transceiver Figure 17. Transmit Clock Timing TCLK TPOS TNEG Table 33. Receive Timing Characteristics Parameter Receive clock capture range Receive clock duty cycle Receive clock pulse width Receive clock pulse width low time Receive clock ...
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Figure 18. Receive Clock Timing Diagram RCLK RPOS RNEG CLKE = 1 RPOS RNEG CLKE = 0 Table 34. JTAG Timing Characteristics Parameter Cycle Time J-TMS/J-TDI to J-TCK rising edge time J-CLK rising to J-TMS/L-TDI hold time J-TCLK falling to ...
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LXT380 — Octal E1 G.703 Transceiver Table 35. Intel Mode Read Timing Characteristics Parameter Address setup time to latch Valid address latch pulse width Latch active to active read setup time Address setup time to RD inactive Address hold time ...
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Figure 20. Non-Multiplexed Intel Mode Read Timing ALE (pulled High INT Tristate RDY Figure 21. Multiplexed Intel Read Timing tVL ALE CS RD tSALR ADDRESS AD7-AD0 INT Tristate RDY Datasheet Octal E1 ...
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LXT380 — Octal E1 G.703 Transceiver Table 36. Intel Mode Write Timing Characteristics Parameter Address setup time to latch Valid address latch pulse width Latch active to active write setup time Address setup time to WR inactive Address hold time ...
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Figure 22. Non-Multiplexed Intel Mode Write Timing A3-A0 (pulled High) ALE CS WR D7-D0 INT tDRDY Tristate RDY Figure 23. Multiplexed Intel Mode Write Timing ALE tVL CS WR tSALW ADDRESS AD7-AD0 INT tDRDY Tristate RDY Datasheet Octal E1 G.703 ...
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LXT380 — Octal E1 G.703 Transceiver Table 37. Motorola Bus Read Timing Characteristics Parameter Address setup time to address or data strobe Address hold time from address or data strobe Valid address strobe pulse width R/W setup time to active ...
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Figure 24. Non-Multiplexed Motorola Mode Read Timing A3-A0 ADDRESS tSAR AS Always High tSRW R D7-D0 INT ACK Datasheet Octal E1 G.703 Transceiver — LXT380 tHAR tSCS tVDS tPDS DATA OUT tDACKP tPACK tHRW tHCS tDZ tINT tDACK ...
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LXT380 — Octal E1 G.703 Transceiver Figure 25. Multiplexed Motorola Mode Read Timing AS tSRW R/W CS tASDS DS tSAR D7-D0 ADDRESS INT ACK Table 38. Motorola Mode Write Timing Characteristics Parameter Address setup time to address strobe Address hold ...
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Table 38. Motorola Mode Write Timing Characteristics (Continued) Parameter Address strobe active to data strobe active delay Data setup time to DS deassertion Data hold time from DS deassertion Valid datastrobe pulse width Inactive data strobe to inactive INT delay ...
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LXT380 — Octal E1 G.703 Transceiver Figure 27. Multiplexed Motorola Mode Write Timing AS tSRW R/W CS tASDS DS tSAS D7-D0 ADDRESS INT ACK Table 39. Serial I/O Timing Characteristics Parameter Rise/fall time any pin SDI to SCLK setup time ...
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Figure 28. Serial Input Timing SCLK t DC LSB SDI CONTROL BYTE Figure 29. Serial Output Timing CLKE = SCLK CS SDO CLKE = SCLK ...
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LXT380 — Octal E1 G.703 Transceiver Table 41. G.703 2.048 Mbit/s Pulse Mask Specifications Test load impedancet Nominal peak mark voltage Nominal peak space voltage Nominal pulse width Ratio of positive and negative pulse amplitudes at center of pulse Ratio ...
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Figure 31. E1 Jitter Tolerance 1000 UI 100 1 1 Datasheet Octal E1 G.703 Transceiver — LXT380 LXT380 typ. ITU G.823, ...
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LXT380 — Octal E1 G.703 Transceiver 5.1 Recommendations and Specifications • G.703 Physical/electrical characteristics of hierarchical digital interfaces • G. 704 functional characteristics of interfaces associated with network nodes • G.735 characteristics of primary PCM multiplex equipment operating at 2048 ...
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Mechanical Specifications Figure 32. LXT380 144 Pin LQFP Package Dimensions 144-Pin Low-Profile Quad Flat Package • Part Number LXT380LE • Extended Temperature Range (-40 ° °C) D/2 E1/2 E1 Dimension † See JEDEC Publication for additional specifications. ...
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LXT380 — Octal E1 G.703 Transceiver Figure 33. LXT380 160 Pin PBGA Package Dimensions 160-Pin Plastic Ball Grid Array • Part Number LXT380BE • Extended Temperature Range (-40 ° °C) 15.00 13.00 ±0.20 4.72 ±0.10 PIN #A1 CORNER ...