DJLXT380LE.B4 Cortina Systems Inc, DJLXT380LE.B4 Datasheet - Page 22

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DJLXT380LE.B4

Manufacturer Part Number
DJLXT380LE.B4
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of DJLXT380LE.B4

Lead Free Status / RoHS Status
Not Compliant

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Part Number
Manufacturer
Quantity
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Part Number:
DJLXT380LE.B4
Manufacturer:
Intel
Quantity:
10 000
LXT380 — Octal E1 G.703 Transceiver
2.2.1
2.2.1.1
2.2.1.2
2.3
22
Loss Of Signal Detector
The loss of signal detector in the LXT380 uses a dedicated analog and digital loss of signal
detection circuit. It is independent of its internal data slicer comparators. and complies to the latest
ITU G.775 recommendations. Under software control, the detector can be configured to comply to
the ETSI ETS 300 233 specifications. In hardware mode, the LXT380 supports LOS per G.775.
Clock and Data Recovery Mode
The receiver monitor loads a digital counter at the RCLK frequency. The count is incremented each
time a zero is received, and reset to zero each time a one (mark) is received. In G.775 mode a
consecutive sequence of 32 zeros sets the LOS signal. The recovered clock is replaced by MCLK at
the RCLK output with a minimum amount of phase errors. (MCLK is required for receive
operation).
In G.775 mode a loss of signal is detected if the signal is below 200 mV (typical) for 32
consecutive pulse intervals. When the received signal reaches 12.5% ones density (4 marks in a
sliding 32-bit period) with no more than 15 consecutive zeros and the signal level exceeds 250 mV
(typical), the LOS flag is reset and another transition replaces MCLK with the recovered clock at
RCLK. RPOS/RNEG will reflect the data content at the receiver input during the entire LOS
detection period for that channel.
In ETSI 300 233 mode a loss of signal is detected if the signal is below 200mV for 2048
consecutive intervals (1 ms.) The LOS condition is cleared and the output pin returns to Low when
the incoming signal has transitions when the signal level is equal or greater than 250mV for more
than 32 consecutive pulse intervals.
Data Recovery Mode
In data recovery mode, the LOS digital timing is derived from a internal self timed circuit. RPOS/
RNEG stay active during loss of signal. The analog LOS detector complies with ITU-G.775
recommendation. The LXT380 monitors the incoming signal amplitude. Any signal below 200mV
for more than 30 s (typical) will assert the corresponding LOS pin. The LOS condition is cleared
when the signal amplitude rises above 250mV. The LXT380 requires more than 10 and less than
255 bit periods to declare a LOS condition in accordance to ITU G.775.
In Service Code Violation Monitoring
In unipolar I/O mode, the LXT380 reports bipolar violations on RNEG/BPV for one RCLK period
for every HDB3 code violation that is not part of the zero code substitution rules.
Datasheet

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