DJLXT380LE.B4 Cortina Systems Inc, DJLXT380LE.B4 Datasheet - Page 52

• Manufacturer Part Number: DJLXT380LE.B4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT380LE.B4

• Lead Free Status / RoHS Status: Not Compliant

LXT380 — Octal E1 G.703 Transceiver
52
Figure 17. Transmit Clock Timing
Table 33. Receive Timing Characteristics
Receive clock capture range
Receive clock duty cycle
Receive clock pulse width
Receive clock pulse width low
time
Receive clock pulse width high
time
Rise/fall time
RPOS/RNEG pulse width
(MCLK=H)
RPOS/RNEG to RCLK rising
setup time
RCLK rising to RPOS/RNEG
hold time
Delay time between RPOS/
RNEG and RCLK
NOTES:
TNEG
TPOS
1. RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and
2. Clock recovery is disabled in this mode.
3. If MCLK = H the receive PLLs are replaced by a simple EXOR circuit.
4. For all digital outputs.
TCLK
minimum RCLK duty cycles are for worst case jitter conditions (0.2UI displacement for E1 per ITU G.823).
Parameter
2
4
1
1
t
SUT
RCKd
t
Sym
t
t
t
PWH
t
PWL
SUR
t
PW
PW
Tr
HR
Min.
447
195
195
200
35
20
50
50
Typ.
±80
488
244
244
244
203
203
50
t
HT
Max.
529
295
295
300
65
5
Unit
ppm
ns
ns
ns
ns
ns
ns
ns
ns
%
@ CL=15 pF
MCLK = H
Test Condition
3
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