DJLXT380LE.B4 Cortina Systems Inc, DJLXT380LE.B4 Datasheet - Page 35

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DJLXT380LE.B4

Manufacturer Part Number
DJLXT380LE.B4
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of DJLXT380LE.B4

Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DJLXT380LE.B4
Manufacturer:
Intel
Quantity:
10 000
Datasheet
Table 10. LOS Status Monitor Register (04H)
Table 11. DFM Status Monitor Register (05H)
Table 12. LOS Interrupt Enable Register (06H)
Table 13. DFM Interrupt Enable Register (07H)
Table 14. LOS Interrupt Status Register (08H)
Table 15. DFM Interrupt Status Register (09H)
Table 16. Software Reset Register (0AH)
Bit
7-0
Bit
7-0
Bit
7-0
Bit
7-0
Bit
7-0
Bit
7-0
Bit
7-0
DFM7-DFM0
RES7-RES0
LOS7-LOS0
DIE7-DIE0
DIS7-DIS0
LIE7-LIE0
LIS7-LIS0
Name
Name
Name
Name
Name
Name
Name
Respective bit(s) are set to “1” every time the LOS processor detects a valid loss of
signal condition in transceivers 7–0. RCLK is used as timing reference. If RCLK is not
available an internal timing signal is used to qualify the LOS condition. Any change in
the state causes an interrupt. On power up the register is set to “0.” All LOS interrupts
are cleared by a single read operation.
Respective bit(s) are set to “1” every time the short circuit monitor detects a valid
secondary output driver short circuit condition in transceivers 7–0. On power-up all the
register bits are set to “0.” All DFM interrupts are cleared by a single read operation.
Transceiver 7–0 LOS interrupts are enabled by writing a “1” to the respective bit. On
power-up all the register bits are set to “0”and all interrupts are disabled.
Transceiver 7–0 DFM interrupts are enabled by writing a “1” to the respective bit. On
power-up all the register bits are set to “0”and all interrupts are disabled.
These bits are set to “1” every time a LOS status change has occurred since the last
cleared interrupt in transceivers 7–0 respectively.
These bits are set to “1” every time a DFM status change has occurred since the last
cleared interrupt in transceivers 7–0 respectively.
Setting a bit to “1” resets the respective transceiver 7–0 respectively. This does not
reset the register (‘0’ clears the reset).
Octal E1 G.703 Transceiver — LXT380
Function
Function
Function
Function
Function
Function
Function
35

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