DJLXT380LE.B4 Cortina Systems Inc, DJLXT380LE.B4 Datasheet - Page 25

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DJLXT380LE.B4

Manufacturer Part Number
DJLXT380LE.B4
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of DJLXT380LE.B4

Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DJLXT380LE.B4
Manufacturer:
Intel
Quantity:
10 000
2.6
2.7
2.7.1
Datasheet
Figure 7. Analog Loopback
Note: Un-terminated lines of adequate length may effectively behave as short-circuits as seen by the
Note: Signals on the RTIP & RRING pins are ignored during analog loopback.
Driver Failure Monitor
The LXT380 transceiver incorporates a unique internal smart power Driver Failure Monitor
(DFM) in parallel with TTIP and TRING that is capable of detecting secondary line shorts. This
feature is available in the serial and parallel host modes but not available in the hardware mode of
operation.
A capacitor, charged via a measure of the driver output current and discharged by a measure of the
maximum allowable current, is used to detect a secondary line short failure. Secondary shorted
lines draw excess current, overcharging the cap. When the capacitor charge deviates outside the
nominal charge window, a driver short circuit fail (DFM) is reported in the respective register by
setting an interrupt. During a long string of spaces, a short-induced overcharge eventually bleeds
off, clearing the DFM flag.
driver and therefore trigger the DMF. Under these circumstances, the user should either disable the
alarm or ensure that the driver is not transmitting marks.
Loopbacks
The LXT380 offers three loopback modes for diagnostic purposes. In hardware mode, the loopback
mode is selected with the LOOPn pins. In host mode, the ALOOP, DLOOP and RLOOP registers
are employed.
Analog Loopback
When selected, the transmitter outputs (TTIP & TRING) are connected internally to the receiver
inputs (RTIP & RRING) as shown in
RNEG pins for the corresponding transceiver.
RNEG
TNEG
RPOS
* If Enabled
TPOS
RCLK
TCLK
Recovery
Timing &
Control
Timing
Figure
7. Data and clock are output at RCLK, RPOS &
Octal E1 G.703 Transceiver — LXT380
TTIP
TRING
RTIP
RRING
25

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