DJLXT380LE.B4 Cortina Systems Inc, DJLXT380LE.B4 Datasheet - Page 4

• Manufacturer Part Number: DJLXT380LE.B4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT380LE.B4

• Lead Free Status / RoHS Status: Not Compliant

LXT380 — Octal E1 Line Interface Unit
6.0
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Mechanical Specifications
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LXT380 Block Diagram ......................................................................................... 7
LXT380 Detailed Block Diagram ........................................................................... 8
LXT380 Low-Profile Quad Flat Package (LQFP) Pin Assignments ...................... 9
LXT380 Plastic Ball Grid Array (PBGA) Package Pin Assignments ................... 10
50% AMI Coding ................................................................................................. 23
External Transmit/Receive Line Circuitry ............................................................ 24
Analog Loopback ................................................................................................ 25
Digital Loopback.................................................................................................. 26
Remote Loopback ............................................................................................... 26
TAOS Data Path ................................................................................................. 27
TAOS with Digital Loopback ............................................................................... 27
TAOS with Analog Loopback .............................................................................. 27
Serial Host Mode Timing..................................................................................... 32
LXT380 JTAG Architecture ................................................................................. 37
JTAG State Diagram ........................................................................................... 39
Analog Test Port Application............................................................................... 45
Transmit Clock Timing ........................................................................................ 51
Receive Clock Timing Diagram........................................................................... 52
JTAG Timing ....................................................................................................... 52
Non-Multiplexed Intel Mode Read Timing ........................................................... 54
Multiplexed Intel Read Timing............................................................................. 54
Non-Multiplexed Intel Mode Write Timing ........................................................... 56
Multiplexed Intel Mode Write Timing ................................................................... 56
Non-Multiplexed Motorola Mode Read Timing.................................................... 58
Multiplexed Motorola Mode Read Timing............................................................ 59
Non-Multiplexed Motorola Mode Write Timing .................................................... 60
Multiplexed Motorola Mode Write Timing ............................................................ 61
Serial Input Timing .............................................................................................. 62
Serial Output Timing ........................................................................................... 62
E1 Mask Template .............................................................................................. 63
E1 Jitter Tolerance .............................................................................................. 64
LXT380 144 Pin LQFP Package Dimensions ..................................................... 66
LXT380 160 Pin PBGA Package Dimensions..................................................... 67
LXT380 Pin Description ...................................................................................... 11
Operation Mode Summary .................................................................................. 28
Operating Mode .................................................................................................. 29
Serial and Parallel Port Register Addresses ....................................................... 33
Register Addresses and Bit Names .................................................................... 33
ID Register (00H) ................................................................................................ 34
Analog Loopback Register (01H) ........................................................................ 34
Remote Loopback Register (02H)....................................................................... 34
TAOS Enable Register (03H).............................................................................. 34
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Datasheet