DJLXT380LE.B4 Cortina Systems Inc, DJLXT380LE.B4 Datasheet - Page 11

• Manufacturer Part Number: DJLXT380LE.B4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT380LE.B4

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
Table 1. LXT380 Pin Description
LQFP
† DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S:
Pin #
1
1
2
3
4
4
5
5
6
Power Supply; N.C.: Not Connected.
PBGA
Pin #
C3
C3
C2
C2
C1
B2
B2
B1
E3
TDATA7
Symbol I/O
RNEG6
TPOS7
RPOS6
TCLK7
RDATA
RCLK6
LOS6
BPV6
6
DO
DO
DO
DO
DO
DO
DI
DI
DI
†
Transmit Positive Data Input.
Transmit Data Input.
Transmit Clock Input. During normal operation, TCLK is active and TPOS
and TNEG are sampled on the falling edge of TCLK. If TCLK is Low, the
output drivers enter a low power High Z mode. If TCLK is High for more than
16 MCLK clock cycles, the pulse shaping circuit is disabled and the transmit
output pulse widths are determined by the TPOS and TNEG duty cycles. If
MCLK does not exist, an analog timer is used to determine if TCLK is High for
at least 12
TCLK Operating Mode:
Clocked Normal operation
Note: The TAOS generator uses MCLK as a timing reference. In order to
Loss of Signal Output. LOS output is High, indicating a loss of signal, when
the incoming signal has no transitions for a specified time interval. The LOS
condition is cleared and the output pin returns to Low when the incoming
signal has sufficient number of transitions in a specified time interval. Details
are in the LOS functional description.
Receive Negative Data Output.
Bipolar Violation Detect Output.
Receive Positive Data Output.
Receive Data Output.
Bipolar Mode:
In clock recovery mode, these pins act as active high bipolar non return to
zero (NRZ) receive signal outputs. A High signal on RPOS corresponds to
receipt of a positive pulse on RTIP/RRING. A High signal on RNEG
corresponds to receipt of a negative pulse on RTIP/RRING. These signals
are valid on the falling or rising edges of RCLK depending on the CLKE input.
In Data recovery Mode these pins act as RZ data receiver outputs. The output
polarity is selectable with CLKE. Active High output polarity when CLKE is
High and Active Low Polarity when CLKE is Low.
RPOS and RNEG will go to the high impedance state when the MCLK pin is
Low.
Unipolar Mode:
In uni-polar mode, LXT380 asserts BPV High if any in-service Line Code
Violation is detected. RDATA acts as the receive data output.
During a LOS condition, RPOS and RNEG will remain active.
Receive Clock Output. This pin provides the recovered clock from the signal
received at RTIP and RRING. Under LOS conditions there is a transition from
RCLK signal (derived from the recovered data) to MCLK signal at the RCLK
output. If MCLK is High, the clock recovery circuit is disabled and RPOS and
RNEG are internally connected to an EXOR that is fed to the RCLK output for
external clock recovery applications. RCLK will be in high impedance state if
the MCLK pin is Low.
H
H
L
assure that the output frequency is within specification limits, MCLK
must have the applicable stability.
TAOS (if MCLK is supplied)
Disable transmit PLL (MCLK is not available)
Driver outputs enter tri-State
seconds in order to enable the above function.
Octal E1 G.703 Transceiver — LXT380
Description
11