DJLXT380LE.B4 Cortina Systems Inc, DJLXT380LE.B4 Datasheet - Page 30

• Manufacturer Part Number: DJLXT380LE.B4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT380LE.B4

• Lead Free Status / RoHS Status: Not Compliant

LXT380 — Octal E1 G.703 Transceiver
2.12.1
2.12.2
30
Note: CS and DS can be connected together in Motorola mode.
generator that controls an Intel and Motorola compatible handshake output signal (RDY/ACK). In
Motorola mode, ACK Low signals valid information is on the data bus. During a write cycle a Low
signal acknowledges the acceptance of the write data. In Intel mode, RDY High signals to the
controlling processor that the bus cycle can be completed. While Low, the microprocessor must
insert wait states. This allows the LXT380 to interface with wait-state capable microcontrollers,
independent of the processor bus speed. To activate this function, a reference clock is required on
the MCLK pin.
An additional active Low interrupt output signal indicates alarm conditions like LOS and DFM to
the microprocessor.
The LXT380 has a 4 bit address bus and provides 15 user accessible 8-bit registers for
configuration, alarm monitoring, and control of the chip.
Motorola Interface
The Motorola interface is selected by asserting the MOT/INTL pin Low. In non-multiplexed mode
the falling edge of DS is used to latch the address information on the address bus. In multiplexed
operation the address on the multiplexed address data bus is latched into the device with the falling
edge of AS. In non-multiplexed mode, AS should be pulled High.
The R/W signal indicates the direction of the data transfer. The DS signal is the timing reference
for all data transfers and typically has a duty cycle of 50%. A read cycle is indicated by asserting R/
W High with a falling edge on DS. A write cycle is indicated by asserting R/W Low with a rising
edge on DS.
Both cycles require the CS signal to be Low and the Address pins to be actively driven by the
microprocessor.
In a write cycle, the data bus is driven by the microprocessor. In a read cycle the bus is driven by
the LXT380.
Intel Interface
The Intel interface is selected by asserting the MOT/INTL pin High. The LXT380 supports non-
multiplexed interfaces with separate address and data pins when MUX is asserted Low, and
multiplexed interfaces when MUX is asserted High. The address is latched in on the falling edge of
ALE. In non-multiplexed mode, ALE should be pulled High. R/W is used as the RD signal and DS
is used as the WR signal. A read cycle is indicated to the LXT380 when the processor asserts RD
Low while the WR signal is held High.
A write operation is indicated to the LXT380 by asserting WR Low while the RD signal is held
High. Both cycles require the CS signal to be Low.
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