IPSERIALLITE Altera, IPSERIALLITE Datasheet - Page 110

• Manufacturer Part Number: IPSERIALLITE
• Manufacturer: Altera

Specifications of IPSERIALLITE

• Lead Free Status / RoHS Status: Not Compliant

Configuring the Simulation
4–6
SerialLite MegaCore Function User Guide
ATLANTIC_TX_CLOCK_PERIOD
DATA_INC_PATTERN
NUM_PRIORITY_PACKETS
NUM_DATA_PACKETS
Table 4–2. SerialLite IP Testbench Parameters (Other Simulator) (Part 1 of 2)
Parameter
Table 4–2
MegaCore Function Version 1.1.0
Minimum
provides information about each parameter and its legal value.
6,400
0
1
1
Maximum
(2^32)-1
(2^32)-1
50,000
1
Default
6,400
10
10
1
This is the main SerialLite
MegaCore clock, which drives
the input CLK and the Atlantic
TX and RX clocks.
The resultant clock also drives
the ALTGXB transceiver. Thus,
this clock determines the data
rate of the high-speed serial
link. The link speed (in Mbps)
is determined as follows:
(1000000/<value>)*20
For each packed on the
regular and priority data ports,
the count restarts at 0 at the
beginning of a new packet.
This parameter affects both
data ports. The current data
value is tracked separately for
each port. The count restarts
when the byte value is 8'hff.
When set to 0, the data
provided in packets is
determined by user input. See
the section
on page
The number of priority data
packets. Controls the number
of packets sent by the Atlantic
generator to the priority data
port.
Only applicable if the priority
data port is enabled.
The number of regular data
packets. Controls the number
of packets sent by the Atlantic
generator to the regular data
port.
Only applicable if the regular
data port is enabled and
packet mode is selected
4–11.
Description
Altera Corporation
“User Packet Data”
August 2005