IPSERIALLITE Altera, IPSERIALLITE Datasheet - Page 53

• Manufacturer Part Number: IPSERIALLITE
• Manufacturer: Altera

Specifications of IPSERIALLITE

• Lead Free Status / RoHS Status: Not Compliant

Specifications
Figure 3–14. Single-Source Clock Configuration
Altera Corporation
August 2005
Atlantic Interface
FPGA 1
MegaCore
SerialLite
Function
Two Clock Sources
Designs often use a two-clock configuration when the two ends of the link
are on different boards, each having its own clock source (see
Figure
frequency, but may differ by a few hundred parts per million (ppm)
because of clock tolerances. Clock compensation is required in this
configuration to ensure that no data is lost on a system that is transmitting
slightly faster than the receiver is processing. If you are using this
configuration, select the Near end and far end use different crystals
option in the Clock Configuration portion of the wizard.
Buffer
MegaCore Function Version 1.1.0
3–15). The two clock sources must have the same nominal
PLL
High-Speed Serial Interface
System Clock
PLL
SerialLite MegaCore Function User Guide
Buffer
MegaCore
SerialLite
Function
FPGA 2
Atlantic Interface
3–21