IPSERIALLITE Altera, IPSERIALLITE Datasheet - Page 89

• Manufacturer Part Number: IPSERIALLITE
• Manufacturer: Altera

Specifications of IPSERIALLITE

• Lead Free Status / RoHS Status: Not Compliant

Specifications
Altera Corporation
August 2005
STATUS_PORT[0]
STATUS_PORT[1]
STATUS_PORT[2]
STATUS_PORT[3]
STATUS_PORT[4]
STATUS_PORT[15..5]
Table 3–41. Status Interface Signals
Name
Output
Output
Output
Output
Output
Output
The status interface is detailed in
Direction
MegaCore Function Version 1.1.0
Link up. Indicates that the local side of the link has been
successfully initialized and is running. It is generated in the
recovered clock domain internally, but is displayed in the system
clock domain. Because the signal crosses domains and is
metastability-hardened, there is a two- to three-cycle latency for the
signal to be asserted and deasserted.
Catastrophic error. Indicates that a catastrophic error was
detected. This signal is asserted the clock cycle after the error is
detected. It is generated in the recovered clock domain internally,
but is displayed in the system clock domain. Because this condition
causes the link to go into an unrecoverable state, this signal is not
metastability-hardened.
Link error. Indicates that a link error was detected. This signal is
asserted high for one clock cycle when the link goes down. It is
generated in the recovered clock domain internally, but is displayed
in the system clock domain. Because the signal crosses domains
and is metastability-hardened, there is a two- to three-cycle latency
for the signal to be asserted and deasserted.
Data error. Indicates that a data error was detected. This signal is
asserted high for one clock cycle for each data error detected.
Within one clock cycle, a single pulse occurs regardless of the
number of errors occurring on the data bus during that clock cycle.
It is generated in the recovered clock domain internally, but is
displayed in the system clock domain. Because the signal crosses
domains and is metastability-hardened, there is a two- to three-
cycle latency for the signal to be asserted and deasserted. In
addition, because of the domain crossing, two consecutive pulses
may occasionally merge into a single pulse. For this reason, use
this signal as a general indicator of the frequency of errors, but not
to collect accurate statistics.
Oversize packet discarded. Used only when the priority data port is
enabled, and when priority packet testing has been enabled.
Indicates that an oversize packet was received at the priority data
port and was discarded. The signal is asserted high for one clock
cycle starting one clock cycle after the oversize packet was
detected. It is generated and displayed in the system clock domain,
and does not cross a domain boundary.
Reserved. Bit 5 is internally connected to the resynchronized
MRESET_N
signal. The other bits are tied to zero.
SerialLite MegaCore Function User Guide
Table
Description
3–41.
3–57