IPSERIALLITE Altera, IPSERIALLITE Datasheet - Page 34

• Manufacturer Part Number: IPSERIALLITE
• Manufacturer: Altera

Specifications of IPSERIALLITE

• Lead Free Status / RoHS Status: Not Compliant

SerialLite Link Configuration
3–2
SerialLite MegaCore Function User Guide
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IP Toolbench provides a fully functional default SerialLite MegaCore
function variation ready for instantiation. The result is a link with the
characteristics shown in
these features.
Bit rate
Lane count
Signal propagation delay
Clock configuration
Lane polarity reversal
Lane order reversal
Regular data port
Data mode
Channel multiplexing (regular data port)
CRC (regular data port)
Priority data port
Retry on error
Flow control
Receive FIFO buffer size
(regular data port)
Transmitter phase-locked loop (PLL)
bandwidth
Receiver PLL bandwidth
Transmitter termination
V
Pre-emphasis
Equalization
Signal detection
Table 3–1. Default SerialLite Link
O D
Whether to use CRC
Whether to implement the retry-on-error feature
Whether to implement flow control
How to size the receive FIFO buffers
Electrical characteristics of the Stratix
MegaCore Function Version 1.1.0
Feature
Table
3–1. The following sections describe all of
3.125 Gbps
1
2.5 ns
Both ends of link use the same clock
source (no clock compensation)
Test only, no reversal
NA (only one lane)
Enabled
Packet
Disabled
Disabled
Disabled
NA (priority data port disabled)
Disabled
Minimum (16 entries)
Low
Low
100 Ω
1,000 mV
0
0
Disabled
®
GX transceivers
Default Configuration
Altera Corporation
August 2005