IPSERIALLITE Altera, IPSERIALLITE Datasheet - Page 41

• Manufacturer Part Number: IPSERIALLITE
• Manufacturer: Altera

Specifications of IPSERIALLITE

• Lead Free Status / RoHS Status: Not Compliant

Specifications
Altera Corporation
August 2005
TMTY[]
THMTY[]
RMTY[]
RHMTY[]
TENA
THENA
RENA
RHENA
Table 3–2. Atlantic Interface Signals (Part 2 of 4)
Name
Input
Output
Input
Input
Direction
Word empty buses. A word-empty bus indicates the number of words that contain no
data on the last cycle of a packet. The system logic places the appropriate value on
the word-empty bus for transmission, and reads its value on reception.
The word-empty bus should always be all zero except on the last cycle of a packet
on the data bus. When the end-of-packet (EOP) signal is asserted, the number of
invalid data bytes on the data bus is specified by the word-empty bus. The width of
the word-empty bus is the number of bits required to represent the maximum
possible number of empty bytes. For example, in a 4-lane link, there are 8 bytes of
data and 7 possible invalid bytes (at least one byte must be valid). The word-empty
bus is therefore 3 bits wide to represent values up to 7.
TMTY[]
end of a packet to be transmitted on the regular data port (packet mode only).
RMTY[]
empty bytes at the end of a packet being received on the regular data port (packet
mode only).
THMTY[]
end of a packet to be transmitted on the priority data port.
RHMTY[]
empty bytes at the end of a packet being received on the priority data port.
Data transfer enable. The data transfer enable signal is driven by the system logic
and controls the data flow across the interface.
When transmitting data, the data transfer enable signal acts as a write-enable from
the system logic to the SerialLite MegaCore function. The system logic asserts the
data transfer enable signal and the data bus signals simultaneously. When the
SerialLite MegaCore function observes the data transfer enable signal asserted on
the rising clock edge, it immediately captures the Atlantic data interface signals.
TENA
THENA
When receiving data, the data transfer enable signal acts as a read-enable from the
system logic to the SerialLite MegaCore function. When the SerialLite MegaCore
function observes the data transfer enable signal asserted on the rising clock edge,
it drives on the next clock edge the Atlantic data interface signals and asserts the
data-valid signal. The system logic captures the Atlantic data interface signals on the
following rising clock edge. If the SerialLite MegaCore function is unable to provide
new data, it deasserts the data valid signal for one or more clock cycles until it is
prepared to drive the valid data interface signals.
RENA
RHENA
acts as a write enable to the regular data port.
acts as a read enable to the regular data port.
acts as a write enable to the priority data port.
acts as a read enable to the priority data port.
is driven by the system logic to specify the number of empty bytes at the
is driven by the SerialLite MegaCore function to specify the number of
MegaCore Function Version 1.1.0
is driven by the system logic to specify the number of empty bytes at the
is driven by the SerialLite MegaCore function to specify the number of
Description
SerialLite MegaCore Function User Guide
3–9