IPSERIALLITE Altera, IPSERIALLITE Datasheet - Page 77

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IPSERIALLITE

Manufacturer Part Number
IPSERIALLITE
Description
Manufacturer
Altera
Datasheet

Specifications of IPSERIALLITE

Lead Free Status / RoHS Status
Not Compliant
Specifications
Altera Corporation
August 2005
Selecting the Proper Pause Duration
Activation of flow control causes a pause in transmission whose duration
you can specify in terms of pause units. Each pause unit is two system
clock cycles. You can specify a pause duration from 1 to 255 pause units
(equivalent to 2 to 510 clock cycles). Set the pause duration based upon
your understanding of the rate at which your system logic consumes the
data received. If a pause is too long, then overall system bandwidth is
reduced. If a pause is too short, it may have to be renewed, which could
result in an overall pause that’s too long.
As an example, assume a theoretical pause needs to be 100 units long. As
a designer, you would not likely know that at design time, so you have to
use your judgment to pick a reasonable value. The effect of a 120-unit
pause would be to cause more delay than needed. However, an 80-unit
delay would result in the pause being renewed with a total of 160 units of
delay, even longer than the 120-unit pause.
Table 3–32
The Receive FIFO Buffers
The receive FIFO buffers are used by the receiving end of the SerialLite
link to store data for presentation to the Atlantic interface and eventual
consumption by the system logic. The appropriate size of the FIFO buffers
depends on a number of factors. The Parameterize - SerialLite MegaCore
function wizard handles these considerations automatically. The default
FIFO buffers generated by the wizard work. You only need consider the
following items if you wish to adjust the size of the FIFO buffers
manually.
The width of the receive FIFO buffers is automatically set by the SerialLite
MegaCore function at two bytes per lane. The depth is the only parameter
that must be set in the wizard. The minimum FIFO buffer size depends on
a number of factors, but the maximum FIFO buffer size theoretically
allowed is 2
practical maximum is determined by the device resources available.
Table 3–32. Flow Control Pause Duration Values
Minimum
1
MegaCore Function Version 1.1.0
shows the flow control pause values.
32
Maximum
entries. No device can provide that much memory, so the
255
Default
255
SerialLite MegaCore Function User Guide
The number of pause units (and half the
number of) system clock cycles for
which the transmitter stops sending
data after it receives a
instruction. Available only if flow control
has been enabled.
Description
PAUSE
3–45

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