IPSERIALLITE Altera, IPSERIALLITE Datasheet - Page 81

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IPSERIALLITE

Manufacturer Part Number
IPSERIALLITE
Description
Manufacturer
Altera
Datasheet

Specifications of IPSERIALLITE

Lead Free Status / RoHS Status
Not Compliant
Specifications
Altera Corporation
August 2005
Minimum
Table 3–34. Regular Data Receive FIFO Buffer Size Values (No Flow Control)
16
Maximum
2
32
Default
Therefore, there must be a certain amount of space left in the receive FIFO
buffer above the threshold to hold the data that arrives during this delay.
This headroom has contributions from the core latency and the wire
latency. The Parameterize - SerialLite MegaCore function wizard
automatically calculates the minimum headroom, displaying the
components of that calculation
to the headroom if you wish.
If a backup PAUSE instruction is desired, then the minimum headroom
must be effectively doubled (compare
because there must be room to accommodate the primary PAUSE
instruction plus the backup PAUSE instruction, in case it’s needed.
Accommodations for the backup PAUSE instruction are automatically
handled by the wizard.
Minimum & Maximum Buffer FIFO Sizes
The maximum FIFO buffer size for either port is 2
more memory than any device can provide, meaning that there is
effectively no limit to the FIFO buffer size within the bounds of available
resources.
The minimum FIFO buffer size requirements are different for the two
data ports. They are also heavily impacted by whether or not flow control
is enabled.
Minimum Regular Data Receive FIFO Buffer
If flow control is not enabled, then the minimum regular data port receive
FIFO buffer size is 16 entries (see
If flow control is enabled, then there is no minimum threshold size (see
Table
frequent triggering of flow control. The minimum headroom is
automatically calculated by the Parameterize - SerialLite MegaCore
function wizard based on core and wire latencies.
16
3–35). However, you should pick a reasonable number to avoid
MegaCore Function Version 1.1.0
Determines the number of entries that are built into the regular data
receive FIFO buffer. Available only if the regular data has been enabled.
Applies only if flow control is disabled or the regular data has not been
selected as a trigger for flow control.
(Figure
SerialLite MegaCore Function User Guide
Table
Description
Figure 3–29
3–30). You can add more margin
3–34).
32
to
entries. This is far
Figure
3–28),
3–49

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