EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 316

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Enhanced PLLs
Figure 1–3. Stratix & Stratix GX Enhanced PLL
Notes to
(1)
(2)
(3)
(4)
1–6
Stratix Device Handbook, Volume 2
INCLK0
INCLK1
External feedback is available in PLLs 5 and 6.
This single-ended external output is available from the g0 counter for PLLs 11 and 12.
These four counters and external outputs are available in PLLs 5 and 6.
This connection is only available on EP1SGX40 Stratix GX devices and EP1S40 and larger Stratix devices. For
example, PLLs 5 and 11 are adjacent and PLLs 6 and 12 are adjacent. The EP1S40 device in the F780 package does
not support PLLs 11 and 12.
Figure
Switch-Over
Circuitry
Clock
1–3:
FBIN
÷ n
(1)
Δt
n
Phase Frequency
Detector (PFD)
Charge
Pump
VCO Phase Selection
Selectable at Each
PLL Output Port
Lock Detect
& Filter
VCO Phase Selection
Affecting All Outputs
Δt
Spectrum
Spread
m
Loop
Filter
÷ m
From Adjacent PLL (4)
VCO
8
Post-Scale
Counters
÷ g 0
÷ g 1
÷ g 2
÷ g 3
÷ e 0
÷ e 1
÷ e 2
÷ e 3
÷ l 0
÷ l 1
Δt
Δt
Δt
Δt
Δt
Δt
Δt
Δt
Δt
Δt
Programmable
Time Delay on
Each PLL Port
4
4
Altera Corporation
I/O Buffers (2)
to I/O or general
routing
Regional
Clocks
Global
Clocks
I/O Buffers (3)
July 2005