EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 712

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

I/O Structure
10–28
Stratix Device Handbook, Volume 2
The differential I/O within Stratix GX also provides dynamic phase
alignment (DPA). DPA enables the differential I/O to operate up to
1 Gbps per channel. DPA automatically and continuously tracks
fluctuations caused by system variations and self-adjusts to eliminate the
phase skew between the multiplied clock and the serial data. The block
contains a dynamic phase selector for phase detection and selection, a
SERDES, a synchronizer, and a data realigner circuit. You can bypass the
dynamic phase aligner without affecting the basic source-synchronous
operation of the channel by using a separate deserializer.
If you compile an APEX II LVDS design that uses clock-data
synchronization (CDS) for a Stratix or Stratix GX device, the Quartus II
software issues a warning during compilation that Stratix and Stratix GX
devices do not support CDS.
Stratix and Stratix GX devices offer a flexible solution using new byte
realignment circuitry to correct for byte misalignment by shifting, or
slipping, data bits. Stratix and Stratix GX devices activate the byte
realignment circuitry when an external pin (rx_data_align) or an
internal custom-made state machine asserts the SYNC node high.
APEX II, APEX 20KE, and APEX 20KCdevices have a dedicated
transmitter clock output pin (LVDSTXOUTCLK). In Stratix and Stratix GX
devices, a transmitter dataout channel with an LVDS clock (fast clock)
generates the transmitter clock output. Therefore, you can drive any
Note to
(1)
EP1SGX10 C
EP1SGX10 D
EP1SGX25 C
EP1SGX25 D
EP1SGX25 F
EP1SGX40 D
EP1SGX40 G
Table 10–10. Number of Dedicated DIfferential Channels in Stratix GX
Devices
Device
For information on channel speeds, see the Stratix GX Device Family Data Sheet
section of the Stratix GX Device Handbook, Volume 1 and the High-Speed
Source-Synchronous Differential I/O Interfaces in Stratix GX Devices chapter of the
Stratix GX Device Handbook, Volume 2.
Table
Note (1)
10–10:
672/1,020
Pin Count
1,020
1,020
1,020
672
672
672
Transceivers
Number of
16
20
4
8
4
8
8
Number of Source-
Altera Corporation
Synchronous
Channels
22
22
39
39
39
45
45
July 2005