EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 685

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Introduction
General
Architecture
Altera Corporation
July 2005
S52012-3.0
Stratix and Stratix GX devices are Altera’s next-generation, system-on-
a-programmable-chip (SOPC) solution. Stratix and Stratix GX devices
simplify the block-based design methodology and bridge the gap
between system bandwidth requirements and programmable logic
performance.
This chapter highlights the new features in the Stratix and Stratix GX
devices and provides assistance when transitioning designs from
APEX
You should be familiar with the APEX II or APEX 20K architecture and
available device features before using this chapter. Use this chapter in
conjunction with the Stratix Device Family Data Sheet section of the Stratix
Device Handbook, Volume 1 or the Stratix GX Device Family Data Sheet
section of the Stratix GX Device Handbook, Volume 1.
Stratix and Stratix GX devices offer many new features and architectural
enhancements. Enhanced logic elements (LEs) and the MultiTrack
interconnect structure offer reduced resource utilization and
considerable design performance improvement. The MultiTrack
interconnect uses DirectDrive
deterministic routing resources for any design block, regardless of its
placement within the device.
All architectural changes between Stratix and Stratix GX and APEX II or
APEX 20K devices described in this section do not require any design
changes. However, you must resynthesize your design and recompile in
the Quartus
TM
II or APEX 20K devices to the Stratix or Stratix GX architecture.
®
II software to target Stratix and Stratix GX devices.
10. Transitioning APEX
TM
technology to ensure the availability of
Designs to Stratix &
Stratix GX Devices
TM
10–1