EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 737

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
July 2005
During configuration and initialization, and before the device enters user
mode, the microprocessor must not drive the CONF_DONE signal low.
1
Figure 11–8
Figure 11–8. PS Configuration Circuit with Microprocessor
PS Configuration Timing
Figure 11–9
Stratix GX devices.
and Stratix GX devices.
Microprocessor
ADDR
If the optional CLKUSR pin is used and nCONFIG is pulled low
to restart configuration during device initialization, you need to
ensure CLKUSR continues toggling during the time nSTATUS is
low (maximum of 40 µs).
Memory
shows the circuit for PS configuration with a microprocessor.
shows the PS configuration timing waveform for Stratix and
DATA0
Table 11–8
10 k Ω
shows the PS timing parameters for Stratix
V CC
Configuring Stratix & Stratix GX Devices
10 k Ω
V CC
Stratix Device Handbook, Volume 2
GND
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
Stratix Device
MSEL2
MSEL1
MSEL0
nCEO
GND
N.C.
V CC
11–19