EP1S10F484I6 Altera, EP1S10F484I6 Datasheet - Page 725

• Manufacturer Part Number: EP1S10F484I6
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484I6

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera
Configuration
Devices
Configuration
Schemes
Altera Corporation
July 2005
f
f
different number of padding bits during programming. However, for any
specific version of the Quartus II software, any design targeted for the
same device has the same configuration file size.
The Altera enhanced configuration devices (EPC16, EPC8, and EPC4
devices) support a single-device configuration solution for high-density
FPGAs and can be used in the FPP and PS configuration schemes. They
are ISP-capable through its JTAG interface. The enhanced configuration
devices are divided into two major blocks, the controller and the flash
memory.
For information on enhanced configuration devices, see the Enhanced
Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet and the Using
Altera Enhanced Configuration Devices chapter in the Configuration
Handbook.
The EPC2 and EPC1 configuration devices provide configuration support
for the PS configuration scheme. The EPC2 device is ISP-capable through
its JTAG interface. The EPC2 and EPC1 can be cascaded to hold large
configuration files.
For more information on EPC2, EPC1, and EPC1441 configuration
devices, see the Configuration Devices for SRAM-Based LUT Devices Data
Sheet.
This section describes how to configure Stratix and Stratix GX devices
with the following configuration schemes:
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PS Configuration
PS configuration of Stratix and Stratix GX devices can be performed using
an intelligent host, such as a MAX
memory, an Altera configuration device, or a download cable. In the PS
scheme, an external host (MAX device, embedded processor,
configuration device, or host PC) controls configuration. Configuration
data is clocked into the target Stratix devices via the DATA0 pin at each
rising edge of DCLK.
PS Configuration with Configuration Devices
PS Configuration with a Download Cable
PS Configuration with a Microprocessor
FPP Configuration
PPA Configuration
JTAG Programming & Configuration
JTAG Programming & Configuration of Multiple Devices
Configuring Stratix & Stratix GX Devices
®
device, microprocessor with flash
Stratix Device Handbook, Volume 2
11–7