Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 100

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Mid-range Memory Chip Select(s) Control
In chip select scheme 1, a user can define the base
address and the total size of the mid-range memory area.
The /MCS0 signal would be active for the lowest quarter
portion of the area defined, starting from the base address.
Each of the /MCS1-/MCS3 signals would be active, corre-
sponding to the successively higher quarter portions of the
total mid-range memory area. In chip select scheme 2, the
mid-range memory area is between the lower and upper
memory areas. The /MCS3-/MCS0 signals can be individu-
ally enabled to go active in refresh transactions.
Mid-range Memory Chip Select Register 0
MA15-MA14 (Match Address Bits 15-14). In chip select
scheme 1, if a match address bit is at logic 1, the corre-
sponding address signal of a memory transaction is com-
pared with the corresponding base address bit for a
match, as a condition for one of /MCS3-/MCS0 to become
active. If the match address bit is at logic 0, the corre-
sponding address signal and base address bit are not
compared (don't care). For example, MA14 determines if
A14 should be compared for a match with BA14. The
values of MA15-MA14 have no effects in chip select
scheme 2.
Reserved bits 5-4. Read as 0s, should write to as 0s.
ERF3-ERF0 (Enable for Refresh Transactions). The mid-
range memory chip select signals can be individually
enabled to go active during refresh transactions. As an
example, /MCS0 goes active in refresh transactions if
ERF0 is programmed at logic 1.
Figure 36. Mid-range Memory Chip Select Register 0
MMCSR0: 00000004H
R/W
7
MA15
0
MA14
0
- -
0
- -
0
ERF3 ERF2 ERF1 ERF0
0
0
0
0
0
<- Reset Value
Enable for Refresh
Transactions
Reserved Bits
Match Address
Bits 15-14
Mid-range Memory Chip Select Register 1
MA23-MA16 (Match Address bits). In chip select scheme
1, if a match address bit is at logic 1, the corresponding
address signal of a memory transaction is compared with
the corresponding base address bit for a match, as a
condition for one of /MCS3-/MCS0 to become active. If the
match address bit is at logic 0, the corresponding address
signal and base address bit are not compared (don't
care). For example, MA23 determines if A23 should be
compared for a match with BA23. The contents of this
register have no effects in chip select scheme 2.
Mid-range Memory Chip Select
Register 2 & 3
Figure 37. Mid-range Memory Chip Select Register 1
Figure 38. Mid-range Memory Chip Select Register 2
MMCSR1: 00000005H
R/W
7
MMCSR2: 00000006H
R/W
7
MA23
BA15
0
0
MA22 MA21 MA20 MA19 MA18 MA17 MA16
BA14
0
0
0
0
--
0
--
0
0
--
0
0
--
0
0
--
0
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0
--
0
0
<- Reset Value
0
Match Address
Bits 23-16
<- Reset Value