Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 21

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PS010002-0708
EXTERNAL INTERFACE (Continued)
Refresh Transactions
A memory refresh transaction is generated by the Z380 MPU refresh controller and can
occur immediately after the final clock cycle of any other transaction. The address during
the refresh transaction is not defined as the CAS-before-RASrefresh cycle is assumed,
which uses the on-chip refresh address generator present on DRAMs. Prior to the first
refresh transaction, a refresh setup cycle is performed to guarantee that the /CAS pre-
charge time is met. This refresh setup cycle is present only prior to the first refresh trans-
action in a burst (Figure 11). Refresh transactions are shown without wait states, with wait
states between T1 and T2, between T2 and T3, and between T3 and T4 (Figures 12-15).
Note that during the refresh cycle the data bus is continuously driven, /MRD and /MWR
remain inactive, /BHEN and /BLEN are active to enable all /CAS signals to the DRAMS,
and those Chip Select signals enabled for DRAM refresh transactions are active.
ADDRESS
BUSCLK
STATUS
/TREFR
/TREFA
/TREFC
/MSIZE
/WAIT
/MWR
DATA
/MRD
Figure 11. Refresh Setup
TPH
TPL
Z380 Microprocessor
Product Specification
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