Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 71
Z8038018FSG
Manufacturer Part Number
Z8038018FSG
Description
IC 16 BIT Z80 MPU 100-QFP
Manufacturer
Zilog
Specifications of Z8038018FSG
Processor Type
Z380
Features
16-Bit, High-Performance Enhanced Z80 CPU
Speed
18MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
100-QFP
Processor Series
Z80380x
Core
Z380
Program Memory Size
64 KB
Maximum Clock Frequency
18 MHz
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Mnemonic
LDCTL SR,HL
LDCTL A,v
LDCTL v,A
LDCTL v,n
SETC LCK
SETC LW
SETC XM
RESC LCK
RESC LW
BTEST
MTEST
Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
L1: In Long Word mode, this instruction loads in 32 bits; dst(31-0)
L9: In Long Word mode, this instruction operates in 32-bits; If A(7) = 0 then HL(31-16) = 0000h else FFFFh
@:
#:
vv
01
10
11
Converts accumulator content into packed BCD following add or subtract with packed BCD operands.
Interrupts are not sampled at the end of EI and DI.
Control Regs
XSR
DSR
YSR
Symbolic
Operation
SR(15-8)
SR(0)
if (LW)
SR(31-16)
else
SR(31-24)
SR(23-16)
v
A
v
SR(1)
Set Lock mode
SR(6)
Set Long word mode
SR(7)
Set Extend mode
SR(1)
Reset Lock mode
SR(6)
Reset Long word mode
Bank Test
S
Z
V
C
Mode test
S
Z
C
A
n
v
SR(16)
SR(24)
SR(0)
SR(7)
SR(6)
SR(8)
SR(1)
HL(0)
1
1
1
0
0
HL(15-8)
HL(31-16)
HL(15-8)
HL(15-8)
S Z x H x V N C
• • x • x • • •
• • x • x • • •
• • x • x • • •
• • x • x • • •
• • x • x • • •
• • x • x • • •
• • x • x • • •
• • x • x • • •
• • x • x • • •
Flags
x • x
x • x • •
src(31-0)
P/
•
76 543 210 HEX Bytes
11 101 101
11 001 000
11 vv1 101
11 010 000
11 vv1 101
11 011 000
11 vv1 101
11 011 010
11 101 101
11 110 111
11 011 101
11 110 111
11 111 101
11 110 111
11 101 101
11 111 111
11 011 101
11 111 111
11 101 01
11 001 111
11 011 101
11 001 111
Opcode
n
DD
DD
DD
ED
DA
ED
ED
ED
C8
D0
D8
FD
CF
CF
F7
F7
F7
FF
FF
# of
2
2
2
3
2
2
2
2
2
2
2
Page 71 of 125
Execute
Time
4
2
4
4
4
4
4
4
4
2
2
Notes
L1
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