Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 103

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Mid-Range Memory Wait Register 2
T1W2-T1W0 (T1 Waits). This binary field defines up to
seven T1 wait states to be inserted in transactions
accessing the mid-range memory area 2 in chip select
scheme 1.
T2W1-T2W0 (T2 Waits). This binary field defines up to
three T2 wait states to be inserted in transactions access-
ing the mid-range memory area 2 in chip select scheme 1.
T3W2-T3W0 (T3 Waits). This binary field defines up to
seven T3 wait states to be inserted in transactions access-
ing the mid-range memory area 2 in chip select scheme 1.
The contents of this register have no effects in chip select
scheme 2.
7
MMWR2: 0000000CH
R/W
T1W2
Figure 44. Mid-Range Memory Waits Register 2
1
T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0
1
1
1
1
1
1
1
0
<- Reset Value
T3 Waits
T2 Waits
T1 Waits
Mid-range Memory Waits Register 3
T1W2-T1W0 (T1 Waits). This binary field defines up to
seven T1 wait states to be inserted in transactions
accessing the mid-range memory area 3 in chip select
scheme 1.
T2W1-T2W0 (T2 Waits). This binary field defines up to
three T2 wait states to be inserted in transactions access-
ing the mid-range memory area 3 in chip select scheme 1.
T3W2-T3W0 (T3 Waits). This binary field defines up to
seven T3 wait states to be inserted in transactions access-
ing the mid-range memory area 3 in chip select scheme 1.
The contents of this register have no effects in chip select
scheme 2.
7
MMWR3: 0000000DH
R/W
T1W2
1
Figure 45. Mid-range Memory Waits Register 3
T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0
1
1
1
1
1
1
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1
0
<- Reset Value
T3 Waits
T2 Waits
T1 Waits