Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 120

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPENDIX A (Continued)
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
no esc
LD SP,nn
LD (nn),A
INC SP **
INC (HL)
DEC (HL)
LD (HL),n
SCF
JR C,e
ADD HL,SP **
LD A,(nn)
DEC SP **
INC A
DEC A
LD A,n
CCF
LD B,B
LD B,C
LD B,D
LD B,E
LD B,H
LD B,L
LD B,(HL)
LD B,A
LD C,B
LD C,C
LD C,D
LD C,E
LD C,H
LD C,L
LD C,(HL)
LD C,A
LD D,B
LD D,C
LD D,D
LD D,E
LD D,H
LD D,L
LD D,(HL)
LD D,A
LD E,B
LD E,C
LD E,D
LD E,E
LD E,H
LD E,L
LD E,(HL)
LD E,A
LD H,B
LD H,C
LD H,D
LD H,E
LD H,H
LD H,L
ED esc
-
LD HL,BC
EX HL,IX
TST (HL)
-
LD (HL),nn
EX A,(HL)
IN0 A,(n)
OUT0 (n),A
-
EX HL,IY
TST A
-
SWAP HL
EX A,A
IN B,(C)
OUT (C),B
SBC HL,BC
LD (nn),BC
NEG
RETN
IM 0
LD I,A
IN C,(C)
OUT (C),C
ADC HL,BC
LD BC,(nn)
MLT BC
RETI
IM 3
LD R,A
IN D,(C)
OUT (C),D
SBC HL,DE
LD (nn),DE
NEGW
RETB
IM 1
LD A,I
IN E,(C)
OUT (C),E
ADC HL,DE
LD DE,(nn)
MLT DE
-
IM 2
LD A,R
IN H,(C)
OUT (C),H
SBC HL,HL
LD (nn),HL
TST m
EXTS
DD esc
LD (HL),IX
INC (IX+d)
DEC (IX+d)
LD (IX+d),n
JR C,ee
ADD IX,SP **
-
LD HL,(BC)
LD HL,(DE)
SWAP IX
INW BC,(C)
OUTW (C),BC
-
-
LD B,IXU
LD B,IXL
LD B,(IX+d)
LD I,HL
-
-
-
-
LD C,IXU
LD C,IXL
LD C,(IX+d)
-
INW DE,(C)
OUTW (C),DE
-
-
LD D,IXU
LD D,IXL
LD D,(IX+d)
LD HL,I
-
-
-
-
LD E,IXU
LD E,IXL
LD E,(IX+d)
-
LD IXU,B
LD IXU,C
LD IXU,D
LD IXU,E
LD IXU,IXU
LD IXU,IXL
LD HL,DE
LD IX,(HL)
LD IX,HL
LD HL,IX
LD HL,(HL)
FD esc
INC (IY+d)
DEC (IY+d)
LD (IY+d),n
ADD IY,SP **
-
SWAP IY
-
-
-
-
LD B,IYU
LD B,IYL
LD B,(IY+d)
-
-
-
-
-
LD C,IYU
LD C,IYL
LD C,(IY+d)
-
-
-
-
-
LD D,IYU
LD D,IYL
LD D,(IY+d)
-
-
-
-
-
LD E,IYU
LD E,IYL
LD E,(IY+d)
-
LD IYU,B
LD IYU,C
LD IYU,D
LD IYU,E
LD IYU,IYU
LD IYU,IYL
LD (HL),IY
JR C,eee
LD (BC),HL
LD (DE),HL
LD HL,HL
LD IY,(HL)
LD IY,HL
LD HL,IY
LD (HL),HL
CB esc
EX H,H’
EX L,L’
-
SRL B
SRL C
SRL D
SRL E
SRL H
SRL L
SRL (HL)
SRL A
BIT 0,B
BIT 0,C
BIT 0,D
BIT 0,E
BIT 0,H
BIT 0,L
BIT 0,(HL)
BIT 0,A
BIT 1,B
BIT 1,C
BIT 1,D
BIT 1,E
BIT 1,H
BIT 1,L
BIT 1,(HL)
BIT 1,A
BIT 2,B
BIT 2,C
BIT 2,D
BIT 2,E
BIT 2,H
BIT 2,L
BIT 2,(HL)
BIT 2,A
BIT 3,B
BIT 3,C
BIT 3,D
BIT 3,E
BIT 3,H
BIT 3,L
BIT 3,(HL)
BIT 3,A
BIT 4,B
BIT 4,C
BIT 4,D
BIT 4,E
BIT 4,H
BIT 4,L
EX C,C’
EX D,D’
EX E,E’
EX A,A’
ED-CB
EX IX,IX’-
EX IY,IY’
-
-
SRLW BC
SRLW DE
SRLW (HL)
SRLW HL
SRLW IX
SRLW IY
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EX DE,DE’
-
EX HL,HL’
DD-CB
-
-
-
-
-
-
LD (SP+d),HL-
SLRW (IX+d)
LD (IX+d),HL
-
-
SRL (IX+d)
-
-
-
-
-
-
-
BIT 0,(IX+d)
-
-
-
-
-
-
-
BIT 1,(IX+d)
-
-
-
-
-
-
-
BIT 2,(IX+d)
-
-
-
-
-
-
-
BIT 3,(IX+d)
-
-
-
-
-
-
-
LD HL,(SP+d)
LD HL,(IX+d)
Page 120 of 125
FD-CB
-
-
-
-
SRLW (IY+d)
-
-
SRL (IY+d)
-
-
-
-
-
-
-
BIT 0,(IY+d)
-
-
-
-
-
-
-
BIT 1,(IY+d)
-
-
-
-
-
-
-
BIT 2,(IY+d)
-
-
-
-
-
-
-
BIT 3,(IY+d)
-
-
-
-
-
-
-
LD (IY+d),HL
-
LD HL,(IY+d)