Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 48

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z380 Microprocessor
Product Specification
This bit controls and reports whether IX or IX' is the cur-
IXP (IXPrime Register Select).
rently active register. IX is selected when this bit is cleared and IX' is selected when this
bit is set. Reset clears this bit and selects IX.
This 2-bit field selects the register set to be used for the
MAINBANK (Main Bank Select).
A, F, BC, DE, HL, A', F', BC', DE' and HL' registers. This field can be set independently
of the register set selection for the other Z380 CPU registers. Reset selects Bank 0 for
these registers.
This bit controls and reports whether
ALT (BC/DE/HL or BC'/DE'/HL' Register Select).
BC/DE/HL or BC'/DE'/HL' is the currently active bank of registers. BC/DE/HL are
selected when this bit is cleared and BC'/DE'/HL' are selected when this bit is set. Reset
clears this bit, selecting BC/DE/HL.
This bit controls the Extended/ Native mode selection for the Z380
XM (Extended Mode).
CPU. This bit is set by the SETC XM instruction, and once set, it can be cleared only by a
reset on the /RESET pin. When this bit is set, the Z380 CPU is in Extended mode. Reset
clears this bit and the Z380 CPU is in Native mode.
LW (Long Word Mode).
This bit controls the Long Word/ Word mode selection for the
Z380 CPU. This bit is set by the SETC LW instruction and cleared by the RESC LW
instruction. When this bit is set, the Z380 CPU is in Long Word mode; when this bit is
cleared, the Z380 CPU is in Word mode. Reset clears this bit. Note that individual instruc-
tions may be executed in either Word or Long Word load and exchange mode, using the
DDIR W and DDIR LW decoder directives.
IEF1 (Interrupt Enable Flag).
This bit is the master Interrupt Enable for the Z380 CPU.
This bit is set by the EI instruction and cleared by the DI instruction. When this bit is set,
interrupts are enabled; when this bit is cleared, interrupts are disabled. Reset clears this bit.
This 2-bit field controls the interrupt mode for the /INT0 interrupt
IM (Interrupt Mode).
request. These bits are controlled by the IM instructions (00 = IM 0, 01 = IM 1, 10 = IM 2,
11 = IM 3). Reset clears both of these bits, selecting Interrupt Mode 0.
This bit controls the Lock/Unlock status of the Z380 CPU. This bit is set by
LCK (Lock).
the SETC LCK instruction and cleared by the RESC LCK instruction. When this bit is set,
no bus requests are accepted, providing exclusive access to the bus by the Z380 CPU.
When this bit is cleared the Z380 CPU will grant bus requests in the normal fashion. Reset
clears this bit.
AFP (AF Prime Register Select).
This bit controls and reports whether AF or AF' is the
currently active pair of registers. AF is selected when this bit is cleared and AF' is selected
when this bit is set. Reset clears this bit and selects AF.
Memory Address Space
The memory address space can be viewed as a string of 4 Gbyte numbered consecutively
in ascending order. The 8-bit byte is the basic addressable element in the Z380 MPU mem-
ory address space. However, there are other addressable data elements; bits, 2-byte words,
bytestrings, and 4-byte words.
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