Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 26

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PS010002-0708
IOCLK (X6)
IOCLK (X8)
IOCLK (X2)
IOCLK (X4)
BUSCLK
EXTERNAL INTERFACE (Continued)
I/O Transactions
I/O transactions move data to or from an external peripheral when the Z380 MPU per-
forms an I/O access. All I/O transactions occur referenced to the IOCLK signal, when it is
a divided-down version of the BUSCLKsignal. BUSCLK may be divided by a factor of
from two to eight to form the IOCLK, under program control. An example of this division
is shown, for the four possible divisors, in Figure 16. Note that the IOCLK divider is syn-
chronized (i.e., starts with a known timing relationship) at the trailing edge of /RESET.
This is discussed in the Reset Section.
The Z380 MPU is unique in that it employs separate control signals for accessing the
memory and I/O. This allows the two interfaces to be optimized independent of one
another. The I/O bus control signals allow direct connection to members of the Z80 family
of peripherals or the Z8500 family of peripherals.
Note that because all I/O bus transactions start on a rising edge of IOCLK, there may be
up to n BUSCLK cycles of latency between the execution unit request for the transaction
and the transaction actually starting, where n is the programmed clock divisor for IOCLK.
This implies that the lowest possible divisor should always be used for IOCLK.
All I/O transactions are four IOCLK cycles long unless extended by Wait states. Wait
states may be inserted between the third and fourth IOCLK cycles in an I/O transaction
and are one IOCLK cycle per wait state. The external /WAIT input is sampled only after
internally-generated wait states are inserted.
Figure 16. IOCLK Timing
Z380 Microprocessor
Product Specification
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