Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 49

IC 16 BIT Z80 MPU 100-QFP

Z8038018FSG

Manufacturer Part Number
Z8038018FSG
Description
IC 16 BIT Z80 MPU 100-QFP
Manufacturer
Zilog
Datasheets

Specifications of Z8038018FSG

Processor Type
Z380
Features
16-Bit, High-Performance Enhanced Z80 CPU
Speed
18MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
100-QFP
Processor Series
Z80380x
Core
Z380
Program Memory Size
64 KB
Maximum Clock Frequency
18 MHz
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8038018FSG
Manufacturer:
Zilog
Quantity:
10 000
PS010002-0708
The size of the data element being addressed depends on the instruction being executed as
well as the Word/Long Word mode. A bit can be addressed by specifying a byte, and a bit
within that byte. Bits are numbered from right to left, with the least significant bit being bit
0 (Figure 35).
The address of a multiple-byte entity is the same as the address of the byte with the lowest
memory address in the entity. Multiple-byte entities can be stored beginning with either
even or odd memory addresses. A word (either 2-byte or 4-byte entity) is aligned if its
address is even; otherwise, it is unaligned. Multiple bus transactions, which may be
required to access multiple-byte entities, can be minimized if alignment is maintained.
The formats of multiple-byte data types are also shown in Figure 35. Note that when a
word is stored in memory, the least significant byte precedes the more significant byte of
the word, as in the Z80 CPU architecture. Also, the lower-addressed byte is present on the
upper byte of the external data bus.
Bits within a byte:
16-bit word at address n:
32-bit word at address n:
Memory addresses:
7
D7-0 (Least Significant Byte)
D15-8
D23-16
D31-24 (Most Significant Byte)
15
6
14
Even address (A0=0)
Least Significant Byte
Least Significant Byte
Most Significant Byte
5
Figure 35. Bit/Byte Ordering Conventions
13
4
12
3
11
2
10
1
9
0
8
7
Address n
Address n+1
Address n
Address n+1
Address n+2
Address n+3
6
Odd address (A0=1)
Most Significant Byte
5
4
3
2
Z380 Microprocessor
Product Specification
1
0
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