Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 8

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PS010002-0708
PIN DESCRIPTION
A31-A0
nals provide a linear memory address space of four gigabytes. The 32-address signals are
also used to access I/O devices.
/BACK
cates that the Z380 MPU has accepted an external bus request and has tri-stated its output
drivers for the address bus, data bus and the bus control signals /TREFR, /TREFA, /
TREFC, /BHEN, /BLEN, /MRD, /MWR, /IORQ, /IORD, and /IOWR. Note that the Z380
MPU cannot provide any DRAM refresh transactions while it is in the bus acknowledge
state.
/BHEN
beginning of a memory, or refresh transaction to indicate that an operation on D15-D8 is
requested. For a 16-bit memory transaction, if /MSIZE is asserted, indicating a byte-wide
memory, another memory transaction is performed to transfer the data on D15-D8, this
time through D15-D8.
beginning of a memory or refresh transaction to indicate that an operation on D7-D0 is
requested. For a 16-bit memory transaction, if /MSIZE is asserted, indicating a byte-wide
memory, only the data on D7-D0 will be transferred during this transaction, and another
transaction will be performed to transfer the data on D15-D8, this time through D7-D0.
/BREQ
master is requesting control of the bus. /BREQ has higher priority than all nonmaskable
and maskable interrupt requests.
BUSCLK
is the reference edge for the majority of other signals generated by the Z380 MPU. BUS-
CLK is a delayed version of the CLK input.
CLKI
at this pin and the Z380 MPU would operate at the CLKI frequency. Alternatively, a crys-
tal up to 20 MHz can be connected across CLKI and CLKO, and the Z380 MPU would
operate at half of the crystal frequency. The two clocking options are controlled by the
CLKsel input.
CLKO
open if an externally generated direct clock is input at the CLKI pin.
CLKsel
to select the direct clock option and should be connected to V
D15-D0
bus is used for data transfer between the Z380 MPU and memory or I/O devices. Note that
for a memory word transfer, the even-addressed (A0 = 0) byte is generally transferred on
D15-D8, and the odd-addressed (A0 = 1) byte on D7-D0 (see the /MSIZE pin description).
/BLEN
Clock/Crystal (input, active High). An externally generated direct clock can be input
Byte High Enable (output, active Low, tri-state). This signal is asserted at the
Crystal (output, active High). Crystal oscillator connection. This pin should be left
Bus Request (input, active Low). When this signal is asserted, an external bus
Byte Low Enable (output, active Low, tri-state). This signal is asserted at the
Address Bus (outputs, activeHigh, tri-state).These non-multiplexed address sig-
Bus Acknowledge (output, active Low, tri-state). This signal, when asserted, indi-
Clock Option Select (input, active High). This input should be connected to VDD
Data Bus (input/outputs, active High, tri-state). This bi-directional 16-bit data
Bus Clock (output, active High, tri-state). This signal, output by the Z380 MPU,
SS
Z380 Microprocessor
Product Specification
for the crystal option.
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