DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet
DS33R41+
Specifications of DS33R41+
Related parts for DS33R41+
DS33R41+ Summary of contents
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GENERAL DESCRIPTION The DS33R41 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over four interleaved T1/E1/J1 lines using a robust, balanced, and programmable inverse multiplexing. Four integrated T1/E1/J1 transceivers provide ...
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DESCRIPTION ................................................................................................................................... 9 2 FEATURE HIGHLIGHTS.................................................................................................................. 11 2.1 G ...................................................................................................................................... 11 ENERAL 2 ICROPROCESSOR NTERFACE 2 INK GGREGATION 2.4 HDLC E M THERNET APPING 2.5 X. INK CCESS 2.6 A HDLC ...
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Full Duplex Flow Control.......................................................................................................................51 9.11.2 Half Duplex Flow Control ......................................................................................................................53 9.11.3 Host-Managed Flow Control .................................................................................................................53 9. THERNET NTERFACE 9.12.1 DTE and DCE Mode .............................................................................................................................56 9.13 E MAC ........................................................................................................................... 57 THERNET 9.13.1 MII Mode ...............................................................................................................................................59 9.13.2 RMII Mode.............................................................................................................................................59 ...
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Receive Packet-Bytes Available ...........................................................................................................95 10.18 L FDL S EGACY UPPORT 10.18.1 Overview ...............................................................................................................................................96 10.18.2 Receive Section ....................................................................................................................................96 10.18.3 Transmit Section ...................................................................................................................................97 10.19 D4/SLC-96 O PERATION 10. INE NTERFACE NIT 10.20.1 LIU Operation........................................................................................................................................98 10.20.2 Receiver ................................................................................................................................................98 10.20.3 ...
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E1 M .................................................................................................................................... 300 ODE 14 OPERATING PARAMETERS ........................................................................................................ 305 14 HERMAL HARACTERISTICS 14.2 MII I ............................................................................................................................ 307 NTERFACE 14.3 RMII I ......................................................................................................................... 309 NTERFACE 14.4 MDIO I ....................................................................................................................... 311 NTERFACE 14.5 T WAN I RANSMIT NTERFACE ...
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Figure 3-1. Quad T1E1 SCT to DS33R41 ...........................................................................................................................15 Figure 6-1. Detailed Block Diagram ....................................................................................................................................18 Figure 6-2. T1/E1/J1 Transceiver Block Diagram ...............................................................................................................19 Figure 6-3. Framer/LIU Interim Signals ...............................................................................................................................20 Figure 7-1. DS33R41 400-Ball BGA Pinout.........................................................................................................................32 Figure 9-1. Clocking for the DS33R41 ................................................................................................................................37 ...
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Figure 13-22. Transmit Side Boundary Timing, TSYSCLK = 2.048MHz (With Elastic Store Enabled) .............................304 Figure 13-23. Transmit IBO Channel Interleave Mode Timing..........................................................................................304 Figure 14-1. Transmit MII Interface Timing .......................................................................................................................307 Figure 14-2. Receive MII Interface Timing ........................................................................................................................308 Figure 14-3. Transmit RMII ...
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Table 2-1. T1-Related Telecommunications Specifications ................................................................................................14 Table 7-1. Detailed Pin Descriptions ...................................................................................................................................21 Table 9-1. Clocking Options for the Ethernet Interface .......................................................................................................36 Table 9-2. Reset Functions .................................................................................................................................................39 Table 9-3. Commands Sent and Received on the IMUX Links ...........................................................................................46 Table 9-4. Command ...
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DESCRIPTION The DS33R41 provides interconnection and mapping functionality between Ethernet packet systems and T1/E1/J1 WAN time-division multiplexed (TDM) systems. The device is composed of a 10/100 Ethernet MAC, packet arbiter, committed information rate controller (CIR), HDLC/X.86 (LAPS) mapper, SDRAM ...
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An 8-bit parallel microcontroller port provides access for control and configuration of all the features of the device. The internal 100MHz SDRAM controller interfaces to a 32-bit wide 128Mbit SDRAM. The SDRAM is used to buffer the data from the ...
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FEATURE HIGHLIGHTS 2.1 General • 400-pin, 27mm BGA package • 1.8V and 3.3V supplies • IEEE 1149.1 JTAG boundary scan • Software access to device ID and silicon revision • Development support includes evaluation kit, driver source code, and ...
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Additional HDLC Controllers in the Integrated T1/E1/J1 Transceiver • Two additional independent HDLC controllers • Fast load and unload features for FIFOs • SS7 support for FISU transmit and receive • Independent 128-byte Rx and Tx buffers with interrupt ...
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Line Interface • Requires a single master clock (MCLK) for both E1 and T1 operation. Master clock can be 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz. Option to use 1.544MHz, 3.088MHz, 6.276MHz, or 12.552MHz for T1-only operation • Fully software configurable ...
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System Interface • Dual two-frame, independent receive and transmit elastic stores Independent control and clocking o Controlled-slip capability with status o Minimum-delay mode supported o • Supports conversion • Ability to pass the T1 F-bit position ...
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APPLICATIONS Bonded Transparent LAN Service LAN Extension Ethernet Delivery over T1/E1/J1 Also see Application Note 3411: DS33Z11—Ethernet LAN to Unframed T1/E1 WAN Bridge for an example of a complete LAN to WAN design. Figure 3-1. Quad T1E1 SCT to ...
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ACRONYMS AND GLOSSARY • BERT - Bit Error Rate Tester • DCE - Data Communication Interface • DTE- Data Terminating Interface • FCS - Frame Check Sequence • HDLC - High Level Data Link Control • MAC - Media ...
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MAJOR OPERATING MODES Microprocessor control is possible through the 8-bit parallel control port and provides configuration for all the features of the device. The Ethernet Link Transport Engine in the device can be configured for HDLC or X.86 encapsulation. ...
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BLOCK DIAGRAMS Figure 6-1. Detailed Block Diagram CLAD TTIP MUX TRING BERT RTIP MUX RRING JTAG2 HDLC HDLC 18 of 335 DS33R41 μP Port CLAD SYSCLKI (RMII MODE) RXD[0:1] RX_CLK CRS_DV RX_ERR REF_CLK REF_CLKO ARBITER TX_EN TXD[0:1] MDC MDIO ...
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers Figure 6-2. T1/E1/J1 Transceiver Block Diagram MCLK2 MCLK1 MASTER CLOCK LOCAL RECEIVE LOOP RTIP LIU BACK JITTER CLOCK & DATA ATTEN. RECOVERY RRING PATH TRANSMIT TTIP LIU JITTER ...
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Framer/LIU Interim Signals The user has limited access to clock and data signals between the framer and LIU on all transceivers as shown in Figure 6-3. Access to the clock and bipolar data signals between the framer and LIU ...
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers 7 PIN DESCRIPTIONS 7.1 Pin Functional Description Note that all digital pins are inout pins in JTAG mode. This feature increases the effectiveness of board level ATPG patterns input, ...
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers NAME PIN CS H16 CST W6 INT E15 COL_DET N20 RX_CRS/ N19 CRS_DV RX_CLK K19 RXD[0] J19 RXD[1] H18 RXD[2] J18 RXD[3] H19 RX_DV K18 RX_ERR K20 TX_CLK L18 TYPE Chip ...
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers NAME PIN TXD[0] L20 TXD[1] M19 TXD[2] M18 TXD[3] M20 TX_EN L19 REF_CLK C20 REF_CLKO G19 DCEDTES L17 RMIIMIIS K13 MDC E20 MDIO F20 SCAS R14 SRAS P15 SDCS R15 TYPE ...
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers NAME PIN SWE T15 SBA[0] R16 SBA[1] W15 SDATA[0] W11 SDATA[1] M15 SDATA[2] Y11 SDATA[3] M14 SDATA[4] U12 SDATA[5] T13 SDATA[6] R13 SDATA[7] W13 SDATA[8] V13 SDATA[9] W12 SDATA[10] V12 SDATA[11] ...
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers NAME PIN RTIP1 N1 RRING1 M1 RTIP2 J13 RRING2 J12 RTIP3 E6 RRING3 F6 RTIP4 T9 RRING4 R9 TTIP1 T1, U1 TRING1 V1, W1 TTIP2 A12, B12 TRING2 A11, B11 TTIP3 ...
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers NAME PIN TRING4 W9, Y9 TSERI1 Y4 TSERI2 B9 TSERI3 J2 TSERI4 R7 TSYSCLK1 H4 TSYSCLK2 J5 TSYSCLK3 A6 TSYSCLK4 Y5 TSSYNC1 W4 TSSYNC2 E13 TSSYNC3 A2 TSSYNC4 N13 TCLKT1 U4 ...
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers NAME PIN ETHERNET MAPPER TRANSMIT SERIAL INTERFACE TSERO K15 TCLKE K14 TBSYNC K16 RSERO1 K4 RSERO2 K9 RSERO3 B5 RSERO4 T7 RSYSCLK1 K1 RSYSCLK2 K10 RSYSCLK3 C6 RSYSCLK4 Y6 RCLK1 W5 ...
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers NAME PIN ETHERNET MAPPER RECEIVE SERIAL INTERFACE RSERI L16 RCLKI L14 RBSYNC L15 RCLKO1 V4 RCLKO2 D12 RCLKO3 C1 RCLKO4 P10 RNEGO1 N4 RNEGO2 G9 RNEGO3 D7 RNEGO4 V6 RPOSO1 N3 ...
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers NAME PIN TSTRST L2 RST H15 TPD D6 MODEC[0], E7, MODEC[1] G15 RLOS/LOTC1 R2 RLOS/LOTC2 C14 RLOS/LOTC3 D4 RLOS/LOTC4 V8 QOVF G18 TYPE HARDWARE AND STATUS PINS Test/Reset. A dual-function pin. ...
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers NAME PIN SYSCLKI Y14 BPCLK1 L3 BPCLK2 G8 MCLK1 K2 MCLK2 L12 JTCLK1 J17 JTDI1 K17 JTRST1 G14 JTDO1 H14 JTMS1 G13 JTCLK2 P9 JTDI2 C7 JTRST2 L13 JTDO2 L10 TYPE ...
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers NAME PIN JTMS2 L11 J16, M13, M17, N14, N15, N16, V N17, P17, R20, DD1.8 T14, V20, W14, Y15, Y18 B16, B17, B19, B20, C19, D18, V DD3.3 D19, D20, E19, ...
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers Figure 7-1. DS33R41 400-Ball BGA Pinout TSSYNC3 RMSYNC3 RCHBLK3 RPOSO3 TSYSCLK3 RSYNC3 RCHCLK3 RSERO3 RCLKO3 TSYNC3 DV ...
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FUNCTIONAL DESCRIPTION The DS33R41 provides interconnection and mapping functionality between Ethernet Packet Systems and T1/E1/J1 WAN Time-Division Multiplexed (TDM) systems. The device is composed of a 10/100 Ethernet MAC, Packet Arbiter, Committed Information Rate Controller (CIR), HDLC/X.86 (LAPS) Mapper, ...
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Both the transmit and receive path have two HDLC controllers. The HDLC controllers transmit and receive data via the framer block. The HDLC controllers can be assigned to any time slot, group of time slots, portion of a time slot, ...
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Read-Write/Data Strobe Modes The processor interface can operate in either read-write strobe mode or data strobe mode. When MODEC = 00 the read-write strobe mode is enabled and a negative pulse on RD performs a read cycle, and a ...
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ETHERNET MAPPER 9.1 Ethernet Mapper Clocks The DS33R41 clocks sources and functions are as follows: • Serial Transmit Data (TCLKE) and Serial Receive Data (RCLKI) clock inputs are used to transfer data from the serial interface. These clocks can ...
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Figure 9-1. Clocking for the DS33R41 CLAD TTIP MUX TRING BERT RTIP MUX RRING JTAG2 HDLC HDLC 37 of 335 μP Port CLAD SYSCLKI REF_CLKO RX_CLK REF_CLK ARBITER TX_CLK MDC JTAG1 SDRAM PORT ...
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Serial Interface Clock Modes The Serial Interface timing is determined by the line clocks. 8.192MHz is the required clock rate for interfacing the IBO bus to Dallas Semiconductor Framers and Single-Chip Transceivers. Both the transmit and receive clocks (TCLKE ...
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Resets and Low-Power Modes The external RST pin and the global reset bit in signal resets the status and control registers on the chip (except the resets all the other flops to their reset values. The processor bus output ...
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Initialization and Configuration EXAMPLE DEVICE INITIALIZATION SEQUENCE: STEP 1: Apply 3.3V supplies, then apply 1.8V supplies. STEP 2: Reset the device by pulling the RST pin low or by using the software reset bits outlined in Section 9.2. Clear ...
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Global Resources In order to maintain software compatibility with the multiport devices in the product family, a set of Global registers are located at 0F0h-0FFh. The global registers include Global resets, global interrupt status, interrupt masking, clock configuration, and ...
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Figure 9-2. Device Interrupt Information Flow Diagram Receive FCS Errored Packet Receive Aborted Packet Receive Invalid Packet Detected Receive Small Packet Detected Receive Large Packet Detected Receive FCS Errored Packet Count Receive Aborted Packet Count Receive Size Violation Packet Count ...
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Serial Interface The Serial Interface consists of physical serial port, IMUX/IBO Formatter, and HDLC/X.86 engine. The Serial Interface supports time-division multiplexed serial data format compatible with Dallas Semiconductor’s 8.192Mbps Channel Interleaved Bus Operation (IBO). The Serial Interface ...
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Figure 9-3. IMUX Interface to T1/E1 Transceivers T1E1 T1E1 LIU Framer T1E1 T1E1 LIU Framer T1E1 Framer LIU T1E1 LIU Framer Figure 9-4. Diagram of Data Transmission with IMUX Operation Data on IBO Bus From TSERO . . . 128 ...
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Microprocessor Requirements Link aggregation requires an external host microprocessor to issue instructions and to monitor the IMUX function of the device. The host microprocessor is responsible for the following tasks to open a transmit channel: • Configuring GL.IMXCN • ...
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IMUX Command Protocol The format for all commands sent and received in Channel 2 of the IBO Serial Interface is shown in The MSB for all commands is a “1.” The next 6 bits contain the actual opcode for ...
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The command and status registers for the IMUX function are detailed below: Table 9-4. Command and Status for the IMUX for Processor Communication REGISTER IMUX Configuration Register IMUX Command Register IMUX Sync Status Register IMUX Sync Latched Status Register IMUX ...
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Out of Frame (OOF) Monitoring Once the links are in synchronization, frame synchronization monitoring is started. The device will declare an out of frame (OOF consecutive sequence errors are received. The device automatically adjusts for single-frame slips ...
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Connections and Queues The multi-port devices in this product family provide bi-directional cross-connections between the multiple Ethernet ports and Serial ports when operating in software mode. A single connection is preserved in this single-port device to provide software compatibility ...
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It is recommended that the user reset the queue pointers for the connection after disconnection. The pointers must be reset before a connection is made. If this disconnect/connect procedure is not followed, incorrect data may be transmitted. The proper procedure ...
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Flow Control Flow control may be required to ensure that data queues do not overflow and packets are not lost. The device allows for optional flow control based on the queue high watermark or through host processor intervention. There ...
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The device will send a ...
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Half Duplex Flow Control Half duplex flow control uses a jamming sequence to exert backpressure on the transmitting node. The receiving node jams the first 4 bytes of a packet that are received from the MAC in order to ...
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Ethernet Interface Port The Ethernet port interface allows for direct connection to an Ethernet PHY. The interface consists of a 10/100Mbps MII/RMII interface and an Ethernet MAC. In RMII operation, the interface contains seven signals with a reference clock ...
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Frames with errors are usually rejected by the device. The user has the option of accepting frames by settings in Receive Frame Rejection Control register (SU.RFRC). The user can program whether to reject or accept frames with the following errors: ...
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DTE and DCE Mode The Ethernet MII/RMII port can be configured for DCE or DTE Mode. When the port is configured for the DTE Mode it can be connected to an Ethernet PHY. In DCE mode, the port can ...
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Figure 9-9. DS33R41 Configured as a DCE in MII Mode 9.13 Ethernet MAC Indirect addressing is required to access the MAC register settings. Writing to the MAC registers requires the SU.MACWD0-SU.MACRD3 registers to be written with 4 bytes of data. ...
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Table 9-8. MAC Control Registers ADDRESS 0000h-0003h 0004h-0007h 0008h-000Bh 0014h-0017h 0018h-001Bh 001Ch-001Fh 0100h-0103h Table 9-9. MAC Status Registers ADDRESS 0200h-0203h 0204h-0207h 0300h-0303h 0308h-030Bh 030Ch-030Fh 0334h-0337h 0338h-033Bh REGISTER MAC Control Register. This register is used for programming full duplex, half duplex, ...
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MII Mode The Ethernet interface can be configured for MII operation by setting the hardware pin RMIIMIIS low. The MII interface consists of 17 pins. For instructions on clocking the Ethernet Interface while in MII mode, see Section 9.1.2. ...
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PHY MII Management Block and MDIO Interface The MII Management Block allows for the host to control PHYs, each with 32 registers. The MII block communicates with the external PHY using 2-wire serial interface composed of ...
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Transmit Packet Processor The Transmit Packet Processor accepts data from the Transmit FIFO performs bit reordering, FCS processing, packet error insertion, stuffing, packet abort sequence insertion, inter-frame padding, and packet scrambling. The data output from the Transmit Packet Processor ...
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Receive Packet Processor The Receive Packet Processor accepts data from the Receive Serial Interface performs packet descrambling, packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, FCS error monitoring, FCS byte extraction, and bit reordering. The ...
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FCS byte extraction discards the FCS bytes. If FCS extraction is enabled, the FCS bytes are extracted from the packet and discarded. If FCS extraction is disabled, the FCS bytes are stored in the receive FIFO with the packet. If ...
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X.86 Encoding and Decoding X.86 protocol provides a method for encapsulating Ethernet Frame onto LAPS. LAPS provides an HDLC-type framing structure for encapsulation of Ethernet frames, but does not inflict dynamic bandwidth expansion as HDLC does. LAPS encapsulated frames ...
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Figure 9-14. X.86 Encapsulation of the MAC field Flag(0x7E) Address(0x04) Control(0x03) 1st Octect of SAPI(0xfe) 2nd Octect of SAPI(0x01) Destination Adrs(DA) Source Adrs(SA) Length/Type MAC Client Data PAD FCS for MAC FCS for LAPS Flag(0x7E) MSB The device will encode ...
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The X86 received frame is aborted if: • If 7d,7E is detected. This is an abort packet sequence in X.86 • Invalid FCS is detected • The received frame has less than 6 octets • Control, SAPI and address field ...
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Committed Information Rate Controller The device provides a CIR provisioning facility. The CIR can be used to restrict the transport of received MAC data to the serial port at a programmable rate. This is shown in the Main Block ...
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INTEGRATED T1/E1/J1 TRANSCEIVERS 10.1 T1/E1/J1 Transceiver Clocks The device contains an on-chip clock synthesizer that generates a user-selectable clock referenced to the recovered receive clock (RCLK). The synthesizer uses a phase-locked loop to generate low-jitter clocks. Common applications include ...
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Table 10-1. T1/E1/J1 Transmit Clock Source TCSS1 TCSS0 0 0 The TCLKT pin (C) is always the source of transmit clock. Switch to the recovered clock (B) when the signal at the TCLKT pin 0 1 fails to transition after ...
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T1 Framer/Formatter Control and Status The T1 framer portion of the transceiver is configured through a set of nine control registers. Typically, the control registers are only accessed when the system is first powered up. Once the transceiver has ...
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers 10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation Receive-side digital-milliwatt (TR.T1RDMR1/2/3) to determine which of the 24 T1 channels of the T1 line going to the backplane should be overwritten with a digital-milliwatt ...
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers 10.5 E1 Framer/Formatter Control and Status The E1 framer portion of the transceiver is configured by a set of four control registers. Typically, the control registers are only accessed when the ...
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Automatic Alarm Generation The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is enabled (TR.E1TCR2.1 = 1), the device monitors the receive-side framer to determine if any of the following conditions are ...
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Loopback Configurations The transceivers have four loopback configurations including Framer, Payload, Local, and Remote loopback. Figure 10-2. depicts a normal signal flow without any loopbacks enabled. Payload loopback may be done on a per-channel basis if both the transmit ...
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Per-Channel Payload Loopback The per-channel loopback registers (PCLRs) determine which channels (if any) from the backplane should be replaced with the data from the receive side or, i.e., off of the line. If this loopback is ...
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Error Counters The transceiver contains four counters that are used to accumulate line-coding errors, path errors, and synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62ms (E1 mode only), or manual. See Error-Counter Configuration Register ...
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers 10.7.2 Path Code Violation Count Register (TR.PCVCR mode, the path code violation count register records Ft, Fs, or CRC6 errors in T1 frames. When the receive side of a ...
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Frames Out-of-Sync Count Register (TR.FOSCR mode, TR.FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This number is useful in ESF applications needing to measure the parameters loss-of-frame count ...
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DS0 Monitoring Function The transceiver has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel ...
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Signaling Operation There are two methods to access receive signaling data and provide transmit signaling data, processor-based (software-based) or hardware-based. Processor-based refers to access through the transmit and receive signaling registers RS1–RS16 and TS1–TS16. Hardware-based refers to the TSIG ...
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Hardware-Based Receive Signaling In hardware-based signaling the signaling data can be obtained from the RSERO pin or the RSIG pin. RSIG is a signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The signaling data, T1 ...
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Figure 10-4. Simplified Diagram of Transmit Signaling Path T1/E1 DATA STREAM ONLY APPLIES TO T1 MODE 10.9.3 Processor-Based Transmit Signaling In processor-based mode, signaling data is loaded into the transmit signaling registers (TS1–TS16) by the host interface. On multiframe boundaries, ...
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E1 Mode In E1 mode, TS16 carries the signaling information. This information can be in either CCS (common channel signaling) or CAS (channel associated signaling) format. The 32 time slots are referenced by two different channel number schemes in ...
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Per-Channel Idle Code Generation Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. When operated in the T1 mode, only the first 24 channels are used by the device, ...
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Idle-Code Programming Examples Example 1 Sets transmit channel 3 idle code to 7Eh. Write TR.IAAR = 02h ;select channel 3 in the array Write TR.PCICR = 7Eh ;set idle code to 7Eh Example 2 Sets transmit channels 3, 4, ...
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Channel Blocking Registers The receive channel blocking registers (TR.RCBR1/TR.RCBR2/TR.RCBR3/TR.RCBR4) and the transmit channel blocking registers (TR.TCBR1/TR.TCBR2/TR.TCBR3/TR.TCBR4) respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low during individual channels. These outputs can ...
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If the buffer empties, then a full frame of data will be repeated at RSERO and the TR.SR5.0 and TR.SR5.1 bits will be set to a one. If the buffer fills, then a full frame of data will be deleted ...
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G.706 Intermediate CRC-4 Updating (E1 Mode Only) The device can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSERI already has the FAS/NFAS, CRC multiframe alignment word, and ...
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T1 Bit-Oriented Code (BOC) Controller The transceiver contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. 10.14.1 Transmit BOC Bits ...
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Additional (Sa) and International (Si) Bit Operation (E1 Only) When operated in the E1 mode, the transceiver provides two methods for accessing the Sa and the Si bits. The first method involves using the internal TR.RAF/TR.RNAF and TR.TAF/TR.TNAF registers ...
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Additional HDLC Controllers in T1/E1/J1 Transceiver This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is configurable for use with time slots, Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). Each ...
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers Table 10-12. HDLC Controller Registers REGISTER TR.H1TC, HDLC #1 Transmit Control Register TR.H2TC, HDLC #2 Transmit Control Register TR.H1RC, HDLC #1 Receive Control Register TR.H2RC, HDLC #2 Receive Control Register TR.H1FC, ...
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FIFO Control The FIFO control register (TR.HxFC) controls and sets the watermarks for the transmit and receive FIFOs. Bits 3, 4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark. When ...
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HDLC Mapping The HDLC controllers must be assigned a space in the T1/E1 bandwidth in which they transmit and receive data. The controllers can be mapped to either the FDL (T1), Sa bits (E1 channels. If mapped ...
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FIFO Information The transmit FIFO buffer-available register indicates the number of bytes that can be written into the transmit FIFO. The count form this register informs the host as to how many bytes can be written into the transmit ...
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Legacy FDL Support (T1 Mode) 10.18.1 Overview To provide backward compatibility to the older DS21x52 T1 device, the transceiver maintains the circuitry that existed in the previous generation of the T1 framer. In new applications recommended that ...
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Transmit Section The transmit section shifts out into the T1 data stream either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the transmit FDL register (TR.TFDL). When a new ...
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Line Interface Unit (LIU) The LIU contains three sections: the receiver that handles clock and data recovery, the transmitter that waveshapes and drives the T1 line, and the jitter attenuator. These three sections are controlled by the line interface ...
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Receive Level Indicator and Threshold Interrupt The device reports the signal strength at RTIP and RRING in 2.5dB increments through RL3–RL0 located in Information Register 2 (TR.INFO2). This feature is helpful when trouble-shooting line-performance problems. The device can initiate ...
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Transmitter The transceiver uses a phase-lock loop along with a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the line. The waveforms created by the device meet the latest ETSI, ITU, ANSI, ...
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MCLK Prescaler A 16.384MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz clock must be applied at MCLK. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specifications require an accuracy of ±32ppm for T1 ...
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Recommended Circuits Figure 10-8. Basic Interface TRANSMIT LINE RECEIVE LINE Note 1: All resistor values are ±1%. Note 2: Resistors R should be set to 60Ω each if the internal receive-side termination feature is enabled. When this feature is ...
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Figure 10-9. E1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 Figure 10-10. T1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ...
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Figure 10-11. Jitter Tolerance 1k 100 10 1 0.1 1 Figure 10-12. Jitter Tolerance (E1 Mode) 1k 100 0.1 1 DEVICE TOLERANCE TR 62411 (DEC. 90) ITU-T G.823 10 100 1k FREQUENCY (Hz) DEVICE TOLERANCE 1.5 MINIMUM ...
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Figure 10-13. Jitter Attenuation (T1 Mode) 0dB -20dB -40dB -60dB 1 Figure 10-14. Jitter Attenuation (E1 Mode) 0 -20 -40 - MODE 10 100 1K FREQUENCY (Hz) TBR12 Prohibited Area E1 MODE 10 100 1k FREQUENCY (Hz) 105 ...
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Figure 10-15. Optional Crystal Connections NOTE 1: C1 AND C2 SHOULD BE 5PF LOWER THAN TWO TIMES THE NOMINAL LOADING CAPACITANCE OF THE CRYSTAL TO ADJUST FOR THE INPUT CAPACITANCE OF THE DEVICE. XTALD MCLK C1 C2 106 of 335 ...
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T1/E1/J1 Transceiver BERT Function Each integrated T1/E1 transceiver contains a BERT. The BERT block can generate and detect pseudorandom and repeating bit patterns used to test and stress data communication links, and it is capable of generating ...
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Figure 10-16. Simplified Diagram of BERT in Network Direction FROM RECEIVE FRAMER PER-CHANNEL AND F-BIT (T1 MODE) MAPPING TO TRANSMIT FRAMER Figure 10-17. Simplified Diagram of BERT in Backplane Direction FROM RECEIVE FRAMER PER-CHANNEL AND F-BIT (T1 MODE) MAPPING TO ...
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BERT Repetitive Pattern Set These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating word pattern Daly pattern. For a repetitive pattern that is fewer than ...
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Payload Error-Insertion Function (T1 Mode Only) An error-insertion function is available in the transceiver and is used to create errors in the payload portion of the T1 frame in the transmit path. This function is only available in T1 ...
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INTERLEAVED PCM BUS OPERATION In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to simplify transport across the system backplane. The transceiver can be configured to allow PCM data to be multiplexed ...
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Figure 11-1. IBO Interconnection Example Integrated T1/E1 Transceivers RSYSCLK1 TSYSCLK1 RSYNC1 TSSYNC1 TSERI1 Framer #1 RSERO1 RSYSCLK2 TSYSCLK2 RSYNC2 TSSYNC2 TSERI2 Framer #2 RSERO2 RSYSCLK3 TSYSCLK3 RSYNC3 TSSYNC3 TSERI3 Framer #3 RSERO3 RSYSCLK4 TSYSCLK4 RSYNC4 TSSYNC4 TSERI4 Framer #4 RSERO4 ...
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Programmable Backplane Clock Synthesizer The transceiver contains an on-chip clock synthesizer that generates a user-selectable clock output on the BPCLK pin, referenced to the recovered receive clock (RCLKn). The synthesizer uses a phase-locked loop to generate low-jitter clocks. Common ...
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DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers 11.4 T1/E1/J1 Transmit Flow Diagrams Figure 11-2. T1/J1 Transmit Flow Diagram HSIE1-3 through PCPR ESCR.4 TESE LBCR1.1 PLB TLINK H1TC.4 HDLC FDL #1 THMS1 H2TC.4 HDLC FDL #2 THMS2 TFDL Tx ...
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From BOC Mux BERT Engine T1TCR2.3 FBCT1 T1TCR2.4 FBCT2 NOEL != 0 ERC.4 CE PEICS1-3 T1CCR1.1 PDE CRC Calculation T1TCR2.7 B8ZSE T1TCR1.1 TBL IOCR1.0 ODF CCR1.4 ODM From ESF From F-bit Mux Yellow Alarm FDL Mux ESF Yellow CRC Mux ...
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Figure 11-3. E1 Transmit Flow Diagram HSIE1-4 through PCPR ESCR.4 TESE LBCR1.1 PLB KEY - PIN - SELECTOR - REGISTER TSIG TSERI Hardware Signaling TX ESTORE Estore Mux TESO Off-Chip Connection TDATA RDATA From E1_rcv_logic Payload HDLC Loopback Mux Engine ...
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From Idle Code Mux Per-Channel Loopback TNAF Sa-bit Mux Si-bit Mux E1TCR1.4 TSIS E1TCR1.0 TCRC4 Si/CRC4 Mux Auto E- E1TCR2.2 AEBE bit Gen Sa4S - Sa8S E1TCR2.5 - E1TCR2.7 E1TCR2.8 ARA TSaCR SSIE1-4 E1TCR1.0 T16S E1TCR1.0 TCRC4 CCR1.6 CRC4R E1TCR2.1 ...
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DEVICE REGISTERS Ten address lines are used to address the register space. The register Map for the device is shown in The addressable range for the device is 0000h to 08FFh. Each Register Section is 64 bytes deep. Global ...
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Register Bit Maps Table 12-2, Table 12-3, Table 12-3, that are reserved are noted with a single dash “—“. All registers not listed are reserved and should be initialized with a value of 00h for proper operation, unless otherwise ...
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Arbiter Register Bit Map Table 12-3. Arbiter Register Bit Map DDR AME IT 040h AR.RQSC1 RQSC1[7] 041h AR.TQSC1 TQSC1[ RQSC1[6] RQSC1[5] RQSC1[4] TQSC1[6] TQSC1[5] TQSC1[4] 120 ...
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Serial Interface Register Bit Map Table 12-4. Serial Interface Register Bit Map DDR AME IT 0C0h Reserved — 0C1h LI.RSTPD — 0C2h LI.LPBK — 0C3h Reserved — 0C4h LI.TPPCL — 0C5h LI.TIFGC TIFG7 0C6h LI.TEPLC ...
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DDR AME IT 104h LI.RPPSR — 105h LI.RPPSRL REPL 106h LI.RPPSRIE REPIE 107h Reserved — 108h LI.RPCB0 RPC7 109h LI.RPCB1 RPC15 10Ah LI.RPCB2 RPC23 10Ch LI.RFPCB0 RFPC7 10Dh LI.RFPCB1 RFPC15 10Eh LI.RFPCB2 RFPC23 10Fh Reserved — ...
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Ethernet Interface Register Bit Map Table 12-5. Ethernet Interface Register Bit Map DDR AME IT 140h SU.MACRADL MACRA7 141h SU.MACRADH MACRA15 142h SU.MACRD0 MACRD7 143h SU.MACRD1 MACRD15 144h SU.MACRD2 MACRD23 145h SU.MACRD3 MACRD31 146h SU.MACWD0 ...
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MAC Register Bit Map Table 12-6. MAC Indirect Register Bit Map DDR AME IT SU.MACCR 0000h — 31:24 0001h DRO 23:16 0002h — 15:8 0003h BOLMT1 BOLMT0 7:0 SU.MACAH 0004h — 31:24 0005h — 23:16 ...
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DDR AME IT Reserved – 111h — initialize to FF Reserved – 112h — initialize to FF Reserved – 113h — initialize to FF SU.RxFrmCtr 200h RXFRMC31 RXFRMC30 RXFRMC29 RXFRMC28 RXFRMC27 RXFRMC26 RXFRMC25 RXFRMC24 31:24 201h ...
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T1/E1/J1 Transceiver Register Bit Map Table 12-7. T1/E1/J1 Transceiver Register Bit Map (Active when CST = DDR AME IT 0 TR.MSTRREG — 1 TR.IOCR1 RSMS 2 TR.IOCR2 RCLKINV 3 TR.T1RCR1 — 4 TR.T1RCR2 — ...
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DDR AME IT 34 TR.E1RCR2 — 35 TR.E1TCR1 TFPT 36 TR.E1TCR2 Reserved 37 TR.BOCC — 38 TR.RSINFO1 CH8 39 TR.RSINFO2 CH16 3A TR.RSINFO3 CH24 3B TR.RSINFO4 — 3C TR.RSCSE1 CH8 3D TR.RSCSE2 CH16 3E TR.RSCSE3 CH24 ...
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DDR AME IT Receive Signaling Bit Format Changes With Operating Mode. See Register Definition. 6D TR.RS14 Receive Signaling Bit Format Changes With Operating Mode. See Register Definition. 6E TR.RS15 Receive Signaling Bit Format Changes With Operating ...
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DDR AME IT A9 TR.H2TCS3 THCS24 AA TR.H2TCS4 THCS32 AB TR.H2TTSBS TCB8SE AC TR.H2RPBA MS AD TR.H2TF THD7 AE TR.H2RF RHD7 AF TR.H2TFBA TFBA7 B0 Reserved — B1 Reserved — B2 Reserved — B3 Reserved — ...
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DDR AME IT E5 TR.BBC3 BBC23 E6 TR.BBC4 BBC31 E7 TR.BEC1 EC7 E8 TR.BEC2 EC15 E9 TR.BEC3 EC23 EA TR.BIC — EB TR.ERC WNOE EC TR.NOE1 C7 ED TR.NOE2 — EE TR.NOEL1 C7 EF TR.NOEL2 — ...
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Global Register Definitions for Ethernet Mapper Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status, framer interrupt status, IBO configuration, MCLK configuration, and BPCLK configuration. These registers are preserved to provide code ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 2: REF_CLKO OFF (REF_CLKO). This bit determines the REF_CLKO output mode REF_CLKO is disabled and outputs an active low signal. 0 ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 4: Serial Interface 1 TX Interrupt Enable (LINE1TIE). Setting this bit to 1 enables an interrupt on LIN1TIS. Bit 0: Serial Interface 1 ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 4: Transmit Queue 1 Interrupt Enable (TQ1IE). Setting this bit to 1 enables an interrupt on TQ1IS. Bit 0: Receive Queue 1 Interrupt ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 0: LINE1[0]. This bit is preserved to provide software compatibility with multiport devices. The LINE1[0] bit selects the Ethernet port that is to ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — T1E1 Default 0 0 Bit 6: T1E1 Mode (T1E1). This bit determines if the IMUX operation is for Mode Mode 1 = ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name ITSYNC4 ITSYNC3 Default 0 0 Bit 7: IMUX Transmit Sync 4 (ITSYNC4). If this bit is set to 1, the device has received a rsync command for the fourth ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name ITSYNCLS4 ITSYNCLS3 Default 0 0 Bit 7: IMUX Transmit Sync Latched Status 4 (ITSYNCLS4). This is a latched status bit for ITSYNC4. Bit 6: IMUX Transmit Sync Latched Status ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TOOFIE4 TOOFIE3 Default 0 0 Bit 7: IMUX Transmit OOF Interrupt Enable 4 (TOOFIE4). Setting this bit to 1 enables an interrupt on TOOFLS4. Bit 6: IMUX Transmit OOF ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 0: BIST Enable (BISTE). If this bit is set the device performs BIST test on the SDRAM. Normal data communication is halted while ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 3: Wrap Type (WT). This bit is used to configure the wrap mode Sequential 1 = Interleave Bits ...
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Register Name: Register Description Register Address: Bit # 7 6 Name SREFT7 SREFT6 Default 0 1 Bits SDRAM Refresh Time Control (SREFT7 to SREFT0). These 8 bits are used to control the SDRAM refresh frequency. The refresh ...
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Arbiter Registers The Arbiter manages the transport between the Ethernet port and the Serial Interface responsible for queuing and dequeuing data to an external SDRAM. The arbiter handles requests from the HDLC and MAC to transfer data ...
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Serial Interface Registers The Serial Interface contains the Serial HDLC transport circuitry and the associated serial port. The Serial Interface register map consists of registers that are common functions, transmit functions, and receive functions. Bits that are underlined are ...
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Transmit HDLC Processor Registers Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Note: The user should take care not to modify this register value during packet error insertion. Bit 5: Transmit ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TIFG7 TIFG6 Default 0 0 Bits Transmit Inter-Frame Gapping (TIFG[7:0]). These eight bits indicate the number of additional flags and bytes of inter-frame fill to be ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name MEIMS TPER6 Default 0 0 Bit 7: Manual Error Insert Mode Select (MEIMS). When 0, the transmit manual error insertion signal (TMEI) will not cause errors to be inserted. ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 0: Transmit Errored Packet Insertion Finished (TEPF). This bit is set when the number of errored packets indicated by the TPEN[7:0] bits in ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TPC7 TPC6 Default 0 0 Bits Transmit Packet Count (TPC[7:0]). Eight bits of 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit # ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TBC23 TBC22 Default 0 0 Bits Transmit Byte Count (TBC[23:16]). Eight bits of 32-bit value. Register description below. Register Name: Register Description: Register Address: Bit # ...
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X.86 Registers X.86 transmit and common registers are used to control the operation of the X.86 encoder and decoder. Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 0: X.86 Encoding ...
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Register Name: Register Description: Register Address: Bit # 7 6 TRSAPIL7 TRSAPIL6 Name Default 0 0 Bits X86 Transmit Receive Control (TRSAPIL7 to TRSAPIL0). This is the address field for the X.86 transmitter and expected value for ...
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Receive Serial Interface Serial Receive Registers are used to control the HDLC Receiver associated with each Serial Interface. Note that throughout this document HDLC Processor is also referred to as “Packet Processor.” The receive packet processor block has 17 ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RMX15 RMX14 Default 0 0 Bits Receive Maximum Packet Size (RMX[15:8]) These 16 bits indicate the maximum allowable packet size in bytes. The size includes the ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name REPL RAPL Default — —- Bit 7: Receive FCS Errored Packet Latched (REPL). This bit is set when a packet with an errored FCS is detected. Bit 6: Receive ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name REPIE RAPIE Default 0 0 Bit 7: Receive FCS Errored Packet Interrupt Enable (REPIE). This bit enables an interrupt if the REPL bit in the LI.RPPSRL register is set. ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RPC7 RPC6 Default 0 0 Bits Receive Packet Count (RPC[7:0]). Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RFPC7 RFPC6 Default 0 0 Bits Receive FCS Errored Packet Count (RFPC[7:0]). Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RAPC7 RAPC6 Default 0 0 Bits Receive Aborted Packet Count (RAPC [7:0]). Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RSPC7 RSPC6 Default 0 0 Bits Receive Size Violation Packet Count (RSPC[7:0]). Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RBC7 RBC6 Default 0 0 Bits Receive Byte Count (RBC[7:0]). Eight bits of a 32-bit value. Register description below. Register Name: Register Description: Register Address: Bit ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name REBC7 REBC6 Default 0 0 Bits Receive Aborted Byte Count (RBC[7:0]). Eight bits of a 32-bit value. Register description below. Register Name: Register Description: Register Address: ...
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Register Name: LI.RHPMUU Register Description: Serial Interface Receive HDLC PMU Update Register Register Address: 120h Bit # 7 6 Name —- — Default 0 0 Bit 0: Receive PMU Update (RPMUU). This signal causes the receive cell/packet processor block performance ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — —- Default 0 0 Bit 3: SAPI Octet Not Equal to LI.RX86S.SAPIHNE generates an interrupt. Bit 2: SAPI Octet Not Equal to LI.RX86S.SAPILNE generates an interrupt. Bit 1: ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name —- —- Default 0 0 Bit 3: Transmit FIFO Overflow for Connection Interrupt Enable (TFOVFIE). If this bit is set, the watermark interrupt is enabled for TFOVFLS. Bit 2: ...
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Ethernet Interface Registers The Ethernet Interface registers are used to configure RMII/MII bus operation and establish the MAC parameters as required by the user. The MAC Registers cannot be addressed directly from the processor port. The registers below are ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name MACRD23 MACRD22 Default 0 0 Bits MAC Read Data 2 (MACRD23 to MACRD16). One of four bytes of data read from the MAC. Valid after a ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name MACD31 MACD30 Defaullt 0 0 Bits MAC Write Data 3 (MACD31 to MACD24). One of four bytes of data to be written to the MAC. Data ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 0: Queue Loopback Enable (QLP). If this bit is set to 1, data from the Ethernet Interface receive queue is looped back to ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 3: No Carrier Queue Flush Bar (NCFQ). If this bit is set to 1, the queue for data passing from Serial Interface to ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name UR EC Default 0 0 Bit 7: Under Run (UR). When this bit is set to 1, the frame was aborted due to a data under run condition of ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name FL7 FL6 Default 0 0 Bits Frame Length (FL[7:0]). These eight bits are the low byte of the length (in bytes) of the received frame, with ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name MF — Default 0 0 Bit 7: Missed Frame (MF). This bit is set the packet is not successfully received from the MAC by the packet ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RMPS7 RMPS6 Default 1 1 Bits Receiver Maximum Frame (RMPS[7:0]). Eight bits of a 16-bit value. Register description below. Register Name: Register Description: Register Address: Bit ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — — Default 0 0 Bit 3: Receive FIFO Overflow Interrupt Enable (RFOVFIE). If this bit is set, the interrupt is enabled for RFOVFLS. Bit 2: Receive Queue Overflow ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name — UCFR Default 0 0 Bit 6: Uncontrolled Control Frame Reject (UCFR). When set to 1, Control Frames other than Pause Frames are allowed. When this bit is equal ...
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MAC Registers The control Registers related to the control of the individual MACs are shown in the following table. The device keeps statistics for the packet traffic sent and received. The register address map is shown in the following ...
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Bit 8: Automatic Pad Stripping (ASTP). When set to 1, all incoming frames with less than 46 byte length are automatically stripped of the pad characters and FCS. Bits 7 and 6: Back-Off Limit (BOLMT[1:0]). These two bits allow the ...
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Register Name: Register Description: Register Address: 0004h: Bit # 31 30 Name Reserved Reserved Default 1 1 0005h: Bit # 23 22 Name Reserved Reserved Default 1 1 0006h: Bit # 15 14 Name PADR47 PADR46 Default 1 1 0007h: ...
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Register Name: Register Description: Register Address: 0014h: Bit # 31 30 Name Reserved Reserved Default 0 0 0015h: Bit # 23 22 Name Reserved Reserved Default 0 0 0016h: Bit # 15 14 Name PHYA4 PHYA3 Default 0 1 0017h: ...
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Register Name: Register Description: Register Address: 0018h: Bit # 31 30 Name Reserved Reserved Default 0 0 0019h: Bit # 23 22 Name Reserved Reserved Default 0 0 001Ah: Bit # 15 14 Name MIID15 MIID14 Default 0 0 001Bh: ...
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Register Name: Register Description: Register Address: 001Ch: Bit # 31 30 Name PT15 PT14 Default 0 0 001Dh: Bit # 23 22 Name PT07 PT06 Default 0 1 001Eh: Bit # 15 14 Name Reserved Reserved Default 0 0 001Fh: ...
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Register Name: Register Description: Register Address: 0100h: Bit # 31 30 Name Reserved Reserved Default 0 0 0101h: Bit # 23 22 Name Reserved Reserved Default 0 0 0102h: Bit # 15 14 Name Reserved Reserved Default 0 0 0103h: ...
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Register Name: Register Description: Register Address: 010Ch: Bit # 31 30 Name Reserved Reserved Default 0 0 010Dh: Bit # 23 22 Name Reserved Reserved Default 0 0 010Eh: Bit # 15 14 Name Reserved Reserved Default 0 0 010Fh: ...
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Register Name: Register Description: Register Address: 0110h: Bit # 31 30 Name Reserved Reserved Default 0 0 0111h: Bit # 23 22 Name Reserved Reserved Default 0 0 0112h: Bit # 15 14 Name Reserved Reserved Default 0 0 0113h: ...
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Register Name: Register Description: Register Address: 0200h: Bit # 31 30 Name RXFRMC31 RXFRMC30 Default 0 0 0201h: Bit # 23 22 Name RXFRMC23 RXFRMC22 Default 0 0 0202h: Bit # 15 14 Name RXFRMC15 RXFRMC14 Default 0 0 0203h: ...
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Register Name: Register Description: Register Address: 0204h: Bit # 31 30 Name RXFRMOK31 RXFRMOK30 Default 0 0 0205h: Bit # 23 22 Name RXFRMOK23 RXFRMOK22 Default 0 0 0206h: Bit # 15 14 Name RXFRMOK15 RXFRMOK14 Default 0 0 0207h: ...
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Register Name: Register Description: Register Address: 0300h: Bit # 31 30 Name TXFRMC31 TXFRMC30 Default 0 0 0301h: Bit # 23 22 Name TXFRMC23 TXFRMC22 Default 0 0 0302h: Bit # 15 14 Name TXFRMC15 TXFRMC14 Default 0 0 0303h: ...
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Register Name: Register Description: Register Address: 0308h: Bit # 31 30 Name TXBYTEC31 TXBYTEC30 Default 0 0 0309h: Bit # 23 22 Name TXBYTEC23 TXBYTEC22 Default 0 0 030Ah: Bit # 15 14 Name TXBYTEC15 TXBYTEC14 Default 0 0 030Bh: ...
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Register Name: Register Description: Register Address: 030Ch: Bit # 31 30 Name TXBYTEOK31 TXBYTEOK30 Default 0 0 030Dh: Bit # 23 22 Name TXBYTEOK23 TXBYTEOK22 Default 0 0 030Eh: Bit # 15 14 Name TXBYTEOK15 TXBYTEOK14 Default 0 0 030Fh: ...
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Register Name: Register Description: Register Address: 0334h: Bit # 31 30 Name TXFRMU31 TXFRMU30 Default 0 0 0335h: Bit # 23 22 Name TXFRMU23 TXFRMU22 Default 0 0 0336h: Bit # 15 14 Name TXFRMU15 TXFRMU14 Default 0 0 0337h: ...
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Register Name: Register Description: Register Address: 0338h: Bit # 31 30 Name TXFRMBD31 TXFRMBD30 Default 0 0 0339h: Bit # 23 22 Name TXFRMBD23 TXFRMBD22 Default 0 0 033Ah: Bit # 15 14 Name TXFRMBD15 TXFRMBD14 Default 0 0 033Bh: ...
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Transceiver Registers Register Name: TR.MSTRREG Register Description: Master Mode Register Register Address: 00h Bit # 7 6 Name — — Default 0 0 Bits 3 and 2: Test Mode Bits (TEST1 and TEST0). Test modes are used to force ...
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Register Name: TR.IOCR1 Register Description: I/O Configuration Register 1 Register Address: 01h Bit # 7 6 Name RSMS RSMS2 Default 0 0 Bit 7: RSYNC Multiframe Skip Control (RSMS). Useful in framing format conversions from D4 to ESF. This function ...
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Register Name: TR.IOCR2 Register Description: I/O Configuration Register 2 Register Address: 02h Bit # 7 6 Name RCLKINV TCLKINV Default 0 0 Bit 7: RCLKn Invert (RCLKINV inversion 1 = inverts signal on RCLKn output. Bit 6: ...
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Register Name: TR.T1RCR1 Register Description: T1 Receive Control Register 1 Register Address: 03h Bit # 7 6 Name — ARC Default 0 0 Bit 6: Auto Resync Criteria (ARC resync on OOF or RCL event 1 = resync ...
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Register Name: TR.T1RCR2 Register Description: T1 Receive Control Register 2 Register Address: 04h Bit # 7 6 Name — RFM Default 0 0 Bit 6: Receive Frame Mode Select (RFM framing mode 1 = ESF framing mode ...
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Register Name: TR.T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address: 05h Bit # 7 6 Name TJC TFPT Default 0 0 Bit 7: Transmit Japanese CRC6 Enable (TJC use ANSI/AT&T/ITU CRC6 calculation (normal operation ...
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Register Name: TR.T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address: 06h Bit # 7 6 Name TB8ZS TSLC96 Default 0 0 Bit 7: Transmit B8ZS Enable (TB8ZS B8ZS disabled 1 = B8ZS enabled Bit 6: Transmit ...
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Register Name: TR.T1CCR1 Register Description: T1 Common Control Register 1 Register Address: 07h Bit # 7 6 Name MCLKS CRC4R Default 0 0 Bit 7: MCLK Source Select (MCLKS). Selects the source of MCLK MCLK is sourced from ...