DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 207

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Input Level Under Threshold (ILUT). This bit is set whenever the input level at RTIP and RRING falls
below the threshold set by the value in TR.CCR4.4 through TR.CCR4.7. The level must remain below the
programmed threshold for approximately 50ms for this bit to be set. This is a double interrupt bit (Section 9.6).
Bit 6: Timer Event (TIMER). Follows the error-counter update interval as determined by the ECUS bit in the error-
counter configuration register (TR.ERCNT).
Bit 5: Receive Signaling Change-of-State Event (RSCOS). Set when any channel selected by the receive
signaling change-of-state interrupt-enable registers (TR.RSCSE1 through TR.RSCSE4) changes signaling state.
Bit 4: Jitter Attenuator Limit Trip Event (JALT). Set when the jitter attenuator FIFO reaches to within 4 bits of its
useful limit. This bit is cleared when read. Useful for debugging jitter attenuation operation.
Bit 3: Line Interface Receive Carrier Loss Condition (LRCL). Set when the carrier signal is lost. This is a double
interrupt bit (Section 9.6).
Bit 2: Transmit Current-Limit Exceeded Condition (TCLE). Set when the 50mA (RMS) current limiter is
activated, whether the current limiter is enabled or not. This is a double interrupt bit (Section 9.6).
Bit 1: Transmit Open-Circuit Detect Condition (TOCD). Set when the device detects that the TTIP and TRING
outputs are open-circuited. This is a double interrupt bit (Section 9.6).
Bit 0: Loss of Line Interface Transmit Clock Condition (LOLITC). Set when TDCLKI has not transitioned for
one channel time. This is a double interrupt bit (Section 9.6).
T1: set on increments of 1 second or 42ms based on RCLKn
E1: set on increments of 1 second or 62.5ms based on RCLKn
ILUT
7
0
TR.SR1
Status Register 1
16h
TIMER
6
0
RSCOS
5
0
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JALT
4
0
LRCL
3
0
TCLE
2
0
TOCD
1
0
LOLITC
0
0