DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 231

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: Manual Error-Counter Update (MECU). When enabled by TR.ERCNT.4, the changing of this bit from a 0 to
a 1 allows the next clock cycle to load the error-counter registers with the latest counts and reset the counters. The
user must wait a minimum of 1.5 RCLKn clock periods before reading the error count registers to allow for proper
update.
Bit 5: Error-Counter Update Select (ECUS)
Bit 4: Error-Accumulation Mode Select (EAMS)
Bit 3: E1 Line-Code Violation Count Register Function Select (VCRFS)
Bit 2: PCVCR Fs-Bit Error-Report Enable (FSBE)
Bit 1: Multiframe Out-of-Sync Count Register Function Select (MOSCRF)
Bit 0: T1 Line-Code Violation Count Register Function Select (LCVCRF)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Line-Code Violation Counter Bits 15 to 8 (LCVC15 to LCVC8). LCV15 is the MSB of the 16-bit code
violation count.
T1 Mode:
E1 Mode:
0 = update error counters once a second
1 = update error counters every 42ms (333 frames)
0 = update error counters once a second
1 = update error counters every 62.5ms (500 frames)
0 = TR.ERCNT.5 determines accumulation time
1 = TR.ERCNT.6 determines accumulation time
0 = count bipolar violations (BPVs)
1 = count code violations (CVs)
0 = do not report bit errors in Fs-bit position; only Ft-bit position
1 = report bit errors in Fs-bit position as well as Ft-bit position
0 = count errors in the framing bit position
1 = count the number of multiframes out-of-sync
0 = do not count excessive 0s
1 = count excessive 0s
LCVC15
—
7
0
7
0
LCVC14
TR.ERCNT
Error-Counter Configuration Register
41h
TR.LCVCR1
Line-Code Violation Count Register 1
42h
MECU
6
0
6
0
LCVC13
ECUS
5
0
5
0
LCVC12
231 of 335
EAMS
4
0
4
0
LCVC11
VCRFS
3
0
3
0
LCVC10
FSBE
2
0
2
0
MOSCRF
LCVC9
1
0
1
0
LCVCRF
LCCV8
0
0
0
0