DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 34

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
Both the transmit and receive path have two HDLC controllers. The HDLC controllers transmit and receive data via
the framer block. The HDLC controllers can be assigned to any time slot, group of time slots, portion of a time slot,
or to FDL (T1) or Sa bits (E1). Each controller has 128-bit FIFOs, thus reducing the amount of processor overhead
required to manage the flow of data. In addition, built-in support for reducing the processor time required handles
SS7 applications.
The backplane interface of the integrated transceivers provides a method of sending and receiving data from the
integrated Ethernet Mapper over an interleaved 8.192MHz TDM (IBO) bus. The Elastic Stores are required for IBO
operation, and manage slip conditions.
The parallel port provides access for control and configuration of all the transceiver’s features. Diagnostic
capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code
generation and detection.
8.1 Processor Interface
Microprocessor control of the DS33R41 is accomplished through the interface pins of the microprocessor port. The
8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the two MODEC[0:1] pins.
When MODEC = 00, bus timing is in Intel mode, as shown in
Figure 14-9
and
Figure
14-10. When MODEC = 01,
bus timing is in Motorola mode, as shown in
Figure 14-11
and
Figure
14-12. The address space is mapped
through the use of 10 address lines, A0 – A9. Multiplexed Mode is not supported on the processor interface.
The Chip Select (CS) pin must be brought to a logic low level to gain read and write access to the microprocessor
port of the Ethernet Mapper. The CST pin must be brought to a logic low level to gain read and write access to the
microprocessor port of the integrated T1/E1 transceivers. With Intel timing selected, the Read (RD) and Write (WR)
pins are used to indicate read and write operations and latch data through the interface. With Motorola timing
selected, the Read-Write (RW) pin is used to indicate read and write operations while the Data Strobe (DS) pin is
used to latch data through the interface.
The interrupt output pin (INT) is an open-drain output that will assert a logic-low level upon a number of software
maskable interrupt conditions. This pin is normally connected to the microprocessor interrupt input. The register
map is shown in
Table
12-1.
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