DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 39

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.2 Resets and Low-Power Modes
The external RST pin and the global reset bit in
signal resets the status and control registers on the chip (except the
resets all the other flops to their reset values. The processor bus output signals are also placed in high-impedance
mode when the RST pin is active (low). The global reset bit
is reset to zero when the external RST pin is active or when a zero is written to it. Allow 5ms after initiating a reset
condition for the reset operation to complete.
The Serial Interface reset bit in
default values, except for the LI.RSTPD.RST bit. The Serial Interface includes the HDLC encoder/decoder, X86
encoder and decoder and the corresponding serial port. The Serial Interface reset bit (LI.RSTPD.RST) stays set
after a one is written to it, but is reset to zero when the global reset signal is active or when a zero is written to it.
Table 9-2. Reset Functions
RESET FUNCTION
Hardware Device Reset
Hardware JTAG Reset
Global Software Reset
Serial interface Reset
Queue Pointer Reset
There are several features in the device to reduce power consumption. The reset bit in the
minimizes power usage in the Serial Interface. Additionally, the RST pin or GL.CR1.RST bit may be held in reset
indefinitely to keep the device in a low-power mode. Note that exiting a reset condition requires re-initialization and
configuration. For the lowest possible standby current, clocks may be externally gated.
LI.RSTPD
LOCATION
RST Pin
JTRST1 Pin
GL.CR1
LI.RSTPD
GL.C1QPR
resets all the status and control registers on the Serial Interface to their
GL.CR1
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COMMENTS
Transition to a logic 0 level resets the
device.
Resets the JTAG test port.
Writing to this bit resets the device.
Writing to this bit resets a Serial
Interface.
Writing to this bit resets the Queue
Pointers
create an internal global reset signal. The global reset
(GL.CR1.
GL.CR1.
RST) stays set after a one is written to it, but
RST bit) to their default values and
LI.RSTPD
register