PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 137

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

15.1
The SPI mode allows 8-bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish communi-
cation, typically three pins are used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS)
15.1.1
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control
(SSPCON1<5:0>) and SSPSTAT<7:6>. These control
bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase
• Clock Edge
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Figure 15-4 shows the block diagram of the MSSP
module when in SPI mode.
(middle or end of data output time)
(output data on rising/falling edge of SCK)
2000 Microchip Technology Inc.
SPI Mode
bits
OPERATION
in
the
SSPCON1
register
FIGURE 15-4:
The MSSP consists of a transmit/receive Shift Register
(SSPSR) and a Buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
have been received, that byte is moved to the SSPBUF
register.
(SSPSTAT<0>) and the interrupt flag bit SSPIF
(PIR2<7>) are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit WCOL (SSPCON1<7>) will be
set. User software must clear the WCOL bit so that it
can be determined if the following write(s) to the
SSPBUF register completed successfully.
SDO
SCK
SDI
SS
Then
Read
SS Control
Select
SMP:CKE
Edge
the
bit0
Enable
Select
Edge
SSPBUF reg
MSSP BLOCK DIAGRAM
(SPI MODE)
Data to TX/RX in SSPSR
Data Direction bit
2
SSPM3:SSPM0
buffer
SSPSR reg
PIC17C7XX
Clock Select
4
2
full
DS30289B-page 137
Write
Prescaler
4, 16, 64
detect
Clock
Shift
TMR2 Output
Data Bus
Internal
2
bit
Tosc
BF