PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 153

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

A typical transmit sequence would go as follows:
a)
b)
c)
d)
e)
f)
g)
h)
i)
j)
k)
l)
FIGURE 15-19:
2000 Microchip Technology Inc.
The user generates a START Condition by set-
ting the START enable bit (SEN) in SSPCON2.
SSPIF is set. The module will wait the required
START time before any other operation takes
place.
The user loads the SSPBUF with address to
transmit.
Address is shifted out the SDA pin until all 8 bits
are transmitted.
The MSSP Module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
The module generates an interrupt at the end of
the ninth clock cycle by setting SSPIF.
The user loads the SSPBUF with eight bits of data.
DATA is shifted out the SDA pin until all 8 bits are
transmitted.
The MSSP Module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register (SSPCON2<6>).
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The user generates a STOP condition by setting
the STOP enable bit PEN in SSPCON2.
Interrupt is generated once the STOP condition
is complete.
SDA
SCL
BRG
Value
BRG
Reload
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
03h
DX
SCL de-asserted but slave holds
SCL low (clock arbitration).
02h
SCL is sampled high, reload takes
place and BRG starts its count.
01h
BRG decrements
(on Q2 and Q4 cycles).
00h (hold off)
DX-1
15.2.8
In I
located in the lower 7 bits of the SSPADD register
(Figure 15-18). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is dec-
remented twice per instruction cycle (T
and Q4 clock.
In I
If Clock Arbitration is taking place, for instance, the
BRG will be reloaded when the SCL pin is sampled
high (Figure 15-19).
FIGURE 15-18:
SSPM3:SSPM0
2
2
SSPM3:SSPM0
C Master mode, the BRG is reloaded automatically.
C Master mode, the reload value for the BRG is
SCL
BAUD RATE GENERATOR
SCL allowed to transition high.
CLKOUT
03h
BAUD RATE GENERATOR
BLOCK DIAGRAM
PIC17C7XX
Reload
Control
02h
BRG Down Counter
SSPADD<6:0>
Reload
DS30289B-page 153
CY
), on the Q2
F
OSC
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