PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 50

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC17C7XX
TABLE 7-3:
DS30289B-page 50
Address
Bank 6
Bank 7
Bank 8
Legend:
Note
Unbanked
10h
11h
12h
13h
14h
15h
16h
17h
10h
11h
12h
13h
14h
15h
16h
17h
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
1:
2:
3:
4:
5:
6:
Unimplemented
Unimplemented
Unimplemented
Unimplemented
DDRH
PORTH
DDRJ
PORTJ
Unimplemented
Unimplemented
Unimplemented
Unimplemented
SSPADD
SSPCON1
SSPCON2
SSPSTAT
SSPBUF
PW3DCL
PW3DCH
CA3L
CA3H
CA4L
CA4H
TCON3
PRODL
PRODH
x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends on condition.
Shaded cells are unimplemented, read as '0'.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose
contents are updated from, or transferred to, the upper byte of the program counter.
The TO and PD status bits in CPUSTA are not affected by a MCLR Reset.
Bank 8 and associated registers are only implemented on the PIC17C76X devices.
This is the value that will be in the port output latch.
When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this port does not rely on these
registers.
On any device RESET, these pins are configured as inputs.
Name
(4)
(4)
SPECIAL FUNCTION REGISTERS (CONTINUED)
SSP Address Register in I
Synchronous Serial Port Receive Buffer/Transmit Register
Capture3 Low Byte
Capture3 High Byte
Capture4 Low Byte
Capture4 High Byte
Data Direction Register for PORTH
Data Direction Register for PORTJ
Low Byte of 16-bit Product (8 x 8 Hardware Multiply)
High Byte of 16-bit Product (8 x 8 Hardware Multiply)
WCOL
GCEN
AN15
SMP
RH7/
Bit 7
DC1
DC9
RJ7
—
—
—
—
—
—
—
—
—
CA4OVF
AKSTAT
SSPOV
AN14
RH6/
Bit 6
CKE
DC0
DC8
RJ6
—
—
—
—
—
—
—
—
TM2PW3
CA3OVF
SSPEN
AKDT
AN13
RH5/
Bit 5
2
DC7
D/A
RJ5
C Slave mode. SSP Baud Rate Reload Register in I
—
—
—
—
—
—
—
—
CA4ED1
AKEN
AN12
RH4/
Bit 4
CKP
DC6
RJ4
—
—
—
—
—
—
—
—
—
P
CA4ED0
SSPM3
RCEN
Bit 3
DC5
RH3
RJ3
—
—
—
—
—
—
—
—
—
S
CA3ED1
SSPM2
Bit 2
PEN
R/W
DC4
RH2
RJ2
—
—
—
—
—
—
—
—
—
CA3ED0
SSPM1
RSEN
Bit 1
DC3
RH1
RJ1
UA
—
—
—
—
—
—
—
—
—
2
C Master mode
2000 Microchip Technology Inc.
PWM3ON
SSPM0
Bit 0
SEN
DC2
RH0
RJ0
BF
—
—
—
—
—
—
—
—
—
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
---- ---- ---- ----
---- ---- ---- ----
---- ---- ---- ----
xx0- ---- uu0- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
-000 0000 -000 0000
---- ---- ---- ----
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
---- ---- ---- ----
---- ---- ---- ----
---- ---- ---- ----
---- ---- ---- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Value on
POR,
BOR
MCLR,
WDT