PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 150

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC17C7XX
15.2.3
While in SLEEP mode, the I
addresses or data and when an address match or com-
plete byte transfer occurs, wake the processor from
SLEEP (if the SSP interrupt is enabled).
TABLE 15-3:
DS30289B-page 150
07h, Unbanked INTSTA
10h, Bank 4
11h, Bank 4
10h. Bank 6
14h, Bank 6
11h, Bank 6
12h, Bank 6
13h, Bank 6
Legend:
Address
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in I
SLEEP OPERATION
PIR2
PIE2
SSPADD
SSPBUF
SSPCON1
SSPCON2
SSPSTAT
Name
REGISTERS ASSOCIATED WITH I
Synchronous Serial Port (I
Synchronous Serial Port Receive Buffer/Transmit Register
SSPIE
WCOL
SSPIF
GCEN
Bit 7
PEIF
SMP
2
C module can receive
ACKSTAT
T0CKIF
SSPOV
BCLIF
BCLIE
Bit 6
CKE
SSPEN
ACKDT
ADIE
Bit 5
ADIF
T0IF
D/A
2
C mode) Address Register
ACKEN
INTF
Bit 4
CKP
—
—
P
2
C OPERATION
SSPM3
CA4IF
CA4IE
RCEN
PEIE
Bit 3
S
15.2.4
A RESET disables the SSP module and terminates the
current transfer.
T0CKIE
SSPM2
CA3IF
CA3IE
Bit 2
PEN
R/W
EFFECTS OF A RESET
SSPM1
TX2IE
RSEN
TX2IF
Bit 1
T0IE
UA
SSPM0
RC2IE
RC2IF
INTE
Bit 0
SEN
BF
2000 Microchip Technology Inc.
2
C mode.
0000 0000
000- 0000
000- 0000
0000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
POR, BOR
MCLR, WDT
0000 0000
000- 0000
000- 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000