PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 210

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC17C7XX
CPFSLT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
Example:
DS30289B-page 210
Before Instruction
After Instruction
operation
Decode
PC
W
If REG
PC
If REG
PC
Q1
Q1
No
register ’f’
operation
Compare f with WREG,
skip if f < WREG
[ label ] CPFSLT
0
(f) – WREG),
skip if (f) < (WREG)
(unsigned comparison)
None
Compares the contents of data memory
location ’f’ to the contents of WREG by
performing an unsigned subtraction.
If the contents of ’f’ are less than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
1
1 (2)
HERE
NLESS
LESS
Read
0011
Q2
Q2
No
=
=
<
=
f
=
255
Address (HERE)
?
WREG;
Address (LESS)
WREG;
Address (NLESS)
CPFSLT REG
:
:
0000
operation
Process
Data
Q3
Q3
No
ffff
f
operation
operation
Q4
Q4
No
No
ffff
DAW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
WREG
REG1
C
DC
WREG
REG1
C
DC
Q1
=
=
=
=
=
=
=
=
register ’f’
Decimal Adjust WREG Register
[label] DAW
0
s
If [ [WREG<7:4> > 9].OR.[C = 1] ].AND.
[WREG<3:0> > 9]
then
WREG<7:4> + 7
If [WREG<7:4> > 9].OR.[C = 1]
then
WREG<7:4> + 6
else
WREG<7:4>
If [WREG<3:0> > 9].OR.[DC = 1]
then
WREG<3:0> + 6
else
WREG<3:0>
C
DAW adjusts the eight-bit value in
WREG, resulting from the earlier addi-
tion of two variables (each in packed
BCD format) and produces a correct
packed BCD result.
s = 0:
s = 1:
1
1
DAW
Read
0010
Q2
0xA5
??
0
0
0x05
0x05
1
0
f
[0,1]
2000 Microchip Technology Inc.
255
REG1, 0
Result is placed in Data
memory location ’f’ and
Result is placed in Data
memory location ’f’.
WREG.
111s
Process
f<7:4>, s<7:4>;
f<3:0>, s<3:0>
Data
Q3
f,s
f<7:4>, s<7:4>;
f<7:4>, s<7:4>;
f<3:0>, s<3:0>;
ffff
register ’f’
and other
specified
register
Write
Q4
ffff