PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 138

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC17C7XX
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
full bit, BF (SSPSTAT<0>), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, bit BF is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the MSSP interrupt is used to
determine when the transmission/reception has com-
pleted. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 15-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
EXAMPLE 15-1:
The SSPSR is not directly readable, or writable and
can only be accessed by addressing the SSPBUF reg-
ister. Additionally, the MSSP status register (SSPSTAT)
indicates the various status conditions.
FIGURE 15-5:
DS30289B-page 138
LOOP BTFSS SSPSTAT, BF
MOVPF SSPBUF, RXDATA ; Save in user RAM
MOVFP TXDATA, SSPBUF ; New data to xmit
MOVLB 6
GOTO
LOOP
SPI Master SSPM3:SSPM0 = 00 xxb
MSb
LOADING THE SSPBUF
(SSPSR) REGISTER
SPI MASTER/SLAVE CONNECTION
PROCESSOR 1
Serial Input Buffer
Shift Register
(SSPBUF)
(SSPSR)
; Bank 6
; Has data been
;
;
;
; No
received
(transmit
complete)?
LSb
SDO
SCK
SDI
Serial Clock
15.1.2
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear bit SSPEN, re-initialize the SSPCON
registers and then set bit SSPEN. This configures the
SDI, SDO, SCK and SS pins as serial port pins. For the
pins to behave as the serial port function, some must
have their data direction bits (in the DDR register)
appropriately programmed. That is:
• SDI is automatically controlled by the SPI module
• SDO must have DDRB<7> cleared
• SCK (Master mode) must have DDRB<6> cleared
• SCK (Slave mode) must have DDRB<6> set
• SS must have PORTA<2> set
Any serial port function that is not desired may be over-
ridden by programming the corresponding data direc-
tion (DDR) register to the opposite value.
15.1.3
Figure 15-5 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
same Clock Polarity (CKP), then both controllers would
send and receive data at the same time. Whether the
data is meaningful (or dummy data) depends on the
application software. This leads to three scenarios for
data transmission:
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
• Master sends dummy data — Slave sends data
SDO
SCK
SDI
ENABLING SPI I/O
TYPICAL CONNECTION
SPI Slave SSPM3:SSPM0 = 010 xb
MSb
Serial Input Buffer
Shift Register
PROCESSOR 2
(SSPBUF)
(SSPSR)
2000 Microchip Technology Inc.
LSb