PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 94

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC17C7XX
10.10.2
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 10-20). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load depen-
dent) before executing the instruction that reads the
values on that I/O port. Otherwise, the previous state of
that pin may be read into the CPU, rather than the
“new” state. When in doubt, it is better to separate
these instructions with a NOP, or another instruction
not accessing this I/O port.
FIGURE 10-20:
FIGURE 10-21:
DS30289B-page 94
PIC17CXXX
Note 1: This is not a capacitor to ground, but the effective
Instruction
Instruction
RB7:RB0
Executed
Fetched
SUCCESSIVE OPERATIONS ON I/O
PORTS
capacitive loading on the trace.
I/O
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
MOVWF PORTB
write to
PORTB
SUCCESSIVE I/O OPERATION
I/O CONNECTION ISSUES
PC
C
(1)
MOVF PORTB,W
MOVWF PORTB
PORTx, PINy
write to
PORTB
PC + 1
V
IL
MOVF PORTB,W
Port pin
sampled here
BSF PORTx, PINy
Q2
PC + 2
NOP
Q3
Figure 10-21 shows the I/O model which causes this
situation. As the effective capacitance (C) becomes
larger, the rise/fall time of the I/O pin increases. As the
device frequency increases, or the effective capaci-
tance increases, the possibility of this subsequent
PORTx read-modify-write instruction issue increases.
This effective capacitance includes the effects of the
board traces.
The best way to address this is to add a series resistor
at the I/O pin. This resistor allows the I/O pin to get to
the desired level before the next instruction.
The use of NOP instructions between the subsequent
PORTx read-modify-write instructions, is a lower cost
solution, but has the issue that the number of NOP
instructions is dependent on the effective capacitance
C and the frequency of the device.
Q4
PC + 3
NOP
NOP
Read PORTx, PINy as low
BSF PORTx, PINz clears the value
to be driven on the PORTx, PINy pin.
Q1
BSF PORTx, PINz
Note:
This example shows a write to PORTB,
followed by a read from PORTB.
Note that:
data setup time = (0.25T
where
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
Q2
T
T
2000 Microchip Technology Inc.
CY
PD
= instruction cycle
= propagation delay
Q3
Q4
CY
- T
PD
)
Q1