PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 175

• Manufacturer Part Number: PIC17C756A-33/L
• Description: 68 PIN, 32 KB OTP, 902 RAM, 50 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC17C756A-33/L

• A/d Inputs: 12-Channel, 10-Bit
• Cpu Speed: 8.25 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 902 Bytes
• Speed: 16 MHz
• Timers: 2-8-bit, 2-16-bit
• Voltage, Range: 3-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

15.3
For standard mode I
resistors R
ing parameters:
• Supply voltage
• Bus capacitance
• Number of connected devices (input current +
The supply voltage limits the minimum value of resistor
R
at V
FIGURE 15-42:
p
leakage current)
2000 Microchip Technology Inc.
due to the specified minimum sink current of 3 mA
OL
Note: I
max = 0.4V for the specified output stages. For
Connection Considerations for
I
2
p
C Bus
also connected.
2
R
C devices with input levels related to V
s
in Figure 15-42 depends on the follow-
2
SAMPLE DEVICE CONFIGURATION FOR I
C bus devices, the values of
SDA
SCL
R
p
R
DD
p
must have one common supply line to which the pull-up resistor is
R
s
V
DD
DEVICE
R
+ 10%
s
example, with a supply voltage of V
V
1.7 k
42. The desired noise margin of 0.1 V
level, limits the maximum value of R
are optional and used to improve ESD susceptibility.
The bus capacitance is the total capacitance of wire,
connections and pins. This capacitance limits the max-
imum value of R
(Figure 15-42).
The SMP bit is the slew rate control enabled bit. This bit
is in the SSPSTAT register and controls the slew rate of
the I/O pins when in I
OL
max = 0.4V at 3 mA, R
V
2
DD
C BUS
as a function of R
p
2
due to the specified rise time
C mode (master or slave).
PIC17C7XX
C
b
= 10 - 400 pF
p
p
min = (5.5-0.4)/0.003 =
is shown in Figure 15-
DD
DS30289B-page 175
s
. Series resistors
= 5V +10% and
DD
for the low