PSB21150FV14XT Infineon Technologies, PSB21150FV14XT Datasheet - Page 121

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

MX/MR Treatment in Error Case
In the master mode the MX/MR bits are under control of the microcontroller through MXC
or MRC, respectively. An abort is indicated by an MAB interrupt or MER interrupt,
respectively.
In the slave mode the MX/MR bits are under control of the device. An abort is always
indicated by setting the MX/MR bit inactive for two or more IOM-2 frames. The controller
must react with EOM.
Figure 67
an example for an abort requested by the transmitter and
for a successful transmission.
Figure 67
Figure 68
Data Sheet
shows an example for an abort requested by the receiver,
IOM -2 Frame No.
MR (DU)
MX (DD)
IOM -2 Frame No.
MX (DU)
MR (DD)
Monitor Channel, Transmission Abort Requested by the Receiver
Monitor Channel, Transmission Abort Requested by the Transmitter
1
0
1
0
1
0
1
0
1
1
2
2
Abort Request from Transmitter
Abort Request from Receiver
121
3
3
4
4
Description of Functional Blocks
Figure 69
5
5
EOM
EOM
6
6
mon_rec-abort.vsd
mon_tx-abort.vsd
shows an example
PSB/PSF 21150
Figure 68
7
7
2003-01-30
IPAC-X
shows