PSB21150FV14XT Infineon Technologies, PSB21150FV14XT Datasheet - Page 197

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

MASKTR
TR_
MODE
4.2.13
Value after reset: FF
The transceiver interrupts LD, RIC, SQC and SQW are enabled (0) or disabled (1).
4.2.14
Value after reset: 000000xx
For general information please refer also to
DCH_INH ... D-Channel Inhibit (NT, LT-S and Int. NT modes only)
Setting this bit to ’1’ has the effect that the S-transceiver blocks the access to the D-
channel on S by inverting the E-bits.
MODE2-0 ... Transceiver Mode
000: TE mode
001: LT-T mode
010: NT mode (without D-channel handler)
011: LT-S mode (without D-channel handler)
110: Intelligent NT mode (with NT state machine and with D-channel handler)
111: Intelligent NT mode (with LT-S state machine and with D-channel handler)
100: reserved
101: reserved
Note: The three modes TE, LT-T and LT-S can be selected by pin strapping (reset
Data Sheet
values for bits TR_MODE.MODE0,1 loaded from pins MODE0,1), all other modes
are programmable only.
7
7
MASKTR - Mask Transceiver Interrupt
TR_MODE - Transceiver Mode Register 1
1
0
H
1
0
B
0
1
1
0
197
DCH_
INH
Chapter
LD
MODE
RIC
2
3.7.5.4.
Detailed Register Description
MODE
SQC
1
0
0
MODE
SQW
PSB/PSF 21150
0
RD/WR (3A)
RD/WR (39)
2003-01-30
IPAC-X