PSB21150FV14XT Infineon Technologies, PSB21150FV14XT Datasheet - Page 232

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PSB21150FV14XT

Manufacturer Part Number
PSB21150FV14XT
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB21150FV14XT

Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
RAH1
RAH2
4.6.7
Value after reset: 00
RAH1 ... Value of the First individual Programmable High Address Byte
In operating modes that provide high byte address recognition, the high byte of the
received address is compared with the individual programmable values in RAH1, RAH2
or group address FC
MHA ... Mask High Address
0: The RAH1 address of an incoming frame is compared with RAH1, RAH2 and Group
1: The RAH1 address of an incoming frame is compared with RAH1 and Group
4.6.8
Value after reset: 00
RAH2 ... Value of the second individual programmable high address byte
See RAH1 register above. RAH1 and RAH2 are used in non-auto mode when a 2-byte
address field has been selected and in the transparent mode 1.
MLA ... Mask Low Address
0:The address of an incoming frame is compared with RAL1, RAL2 and Group
Address.
1:The address of an incoming frame is compared with RAL1 and Group
Address. RAL1 can be masked with RAL2 thereby bitpositions of RAL1 are not
compared if they are set to ’1’ in RAL2.
Data Sheet
Address.
Address. RAH1 can be masked with RAH2 thereby bitpositions of RAH1 are not
compared if they are set to ’1’ in RAH2.
7
7
RAH1 - RAH1 Register
RAH2 - RAH2 Register
H
H
H
/FE
H
.
RAH1
RAH2
232
Detailed Register Description
0
0
0
0
MHA
MLA
PSB/PSF 21150
WR (75/85)
WR (76/86)
2003-01-30
IPAC-X

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