PSB21150FV14XT Infineon Technologies, PSB21150FV14XT Datasheet - Page 83

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

IPAC-X
PSB/PSF 21150
Description of Functional Blocks
3.5.2.2
States (LT-S)
G1 Deactivated
The transceiver is not transmitting. There is no signal detected on the S/T-interface, and
no activation command is received in the C/I channel. The clocks are deactivated if
MODE1-CFS is set to 1. Activation is possible from the S/T interface and from the IOM-2
interface.
G2 Pending Activation
As a result of an INFO 0 detected on the S/T line or an ARD command, the transceiver
begins transmitting INFO 2 and waits for reception of INFO 3. The timer to supervise
reception of INFO 3 is to be implemented in software. In case of an ARL command, loop
2 is closed.
G3 Activated
Normal state where INFO 4 is transmitted to the S/T-interface. The transceiver remains
in this state as long as neither a deactivation nor a test mode is requested, nor the
receiver looses synchronism.
When receiver synchronism is lost, INFO 2 is sent automatically. After reception of
INFO 3, the transmitter keeps on sending INFO 4.
G2 Lost Framing
This state is reached when the transceiver has lost synchronism in the state G3
activated.
G4 Pending Deactivation
This state is triggered by a deactivation request DR. It is an unstable state: indication DI
(state “G4 wait for DR.”) is issued by the transceiver when:
either INFO0 is received for a duration of 16 ms,
or an internal timer of 32 ms expires.
G4 Wait for DR
Final state after a deactivation request. The transceiver remains in this state until DC is
issued.
Unconditional States
Test Mode - SSP
Single alternating pulses are sent on the S/T-interface.
Data Sheet
83
2003-01-30