PSB21150FV14XT Infineon Technologies, PSB21150FV14XT Datasheet - Page 46

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Timer 1
The host controls the timer 1 by setting bit CMDRD.STI to start the timer and by writing
register TIMR1 to stop the timer. After time period T1 an interrupt (AUXI.TIN1) is
generated continuously if CNT=7 or a single interrupt is generated after timer period T if
CNT<7
Figure 14
Timer 2
The host starts and stops timer 2 in TIMR2.CNT
is operating in count down mode, for TIMR2.TMD=1 a periodic interrupt AUXI.TIN2 is
generated. The timer length (for count down timer) or the timer period (for periodic timer),
respectively, can be configured to a value between 1 - 63 ms (TIMR2.CNT).
Figure 15
Data Sheet
TIMR1
(Figure
7 6 5 4 3 2 1 0
CNT
Timer 1 Register
Timer 2 Register
14).
TIMR2
VALUE
TMD 0
7
6
5
Retry Counter
0 ... 6 : Count Down Timer
Expiration Period
T1 = (VALUE + 1) x 0.064 sec
24
4
H
7 : Periodic Timer
3
CNT
2
1
0
46
Timer Mode
0 : Count Down Timer
1 : Periodic Timer
Timer Count
1 ... 63 : 1 ... 63 ms
65
H
(Figure
0 : Timer off
Description of Functional Blocks
15). If TIMR2.TMD=0 the timer
T = CNT x 2.048 sec + T1
T = T1
21150_14
PSB/PSF 21150
2003-01-30
IPAC-X
21150_14