PSB21150FV14XT Infineon Technologies, PSB21150FV14XT Datasheet - Page 141

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

INT0, INT1
In all modes two pins can be used as programmable I/O with optional interrupt input
capability (default after reset, i.e. both interrupts masked).
The INT0/1 pins are general input or output pins like AUX0-5 (see description above).
In addition to that, as inputs they can generate an interrupt to the host (AUXI.INT0/1)
which is maskable in AUXM.INT0/1. The interrupt input is either edge or level triggered
(ACFG2.EL0/1).
As outputs both pins can directly be connected to an LED with preresistor.
For both pins AUX6/7 internal pull-up resistors are provided if the pin is configured as
input or as output with open drain chracteristic. The internal pull-ups are disabled if
output mode with push/pull characteristic is selected.
SGO
AUX7 provides the additional capability to output the S/G bit from the IOM-2 interface by
setting ACFG2.A7SEL=1.
MBIT
If ACFG2.A4SEL is set to “1” the pin AUX4 is used for Multiframe Synchronizstion (see
Chapter
LT-T modes it is used as M-Bit output and in LT-S, NT and Int. NT mode it is used as
M-Bit input.
CH0, CH1, CH2
In linecard mode one FSC frame is a multiplex of up to eight IOM-2 channels, each of
them consisting of B1-, B2-, MONITOR-, D- and C/I-channel and MR- and MX-bits.
So in LT-T and LT-S mode one of eight channels on the IOM-2 interface is selected by
CH0-2. These pins must be strapped to VDD or VSS according to
Table 16
CH2
0
0
0
0
1
1
1
1
Data Sheet
3.3.3) and all configuration as general purpose I/O pin is don’t care. In TE and
IOM-2 Channel Selection
CH1
0
0
1
1
0
0
1
1
CH0
0
1
0
1
0
1
0
1
141
Channel on IOM-2
0
1
2
3
4
5
6
7
Description of Functional Blocks
Table
PSB/PSF 21150
16.
2003-01-30
IPAC-X